Processor: ADSP-SC573
The ADSP-SC57x processor includes two SHARC core i.e., Core 1 and Core 2. Each core supports four flag pins, which can be used for input or output signals. See the image below for reference.
The SHARC+ core can directly set, clear, or read these flag pins using direct instruction support. The status of each pin is shown in the REGF_FLAGS register.
When a flag pin is set as an output, the processor sends a high signal if the corresponding bit in the REGF_FLAGS register is turned on.
The direction of each pin (input or output) is controlled by specific bits:FLG0O, FLG1O, FLG2O, and FLG3O in the REGF_FLAGS register.
In the REGF_FLAGS register bit definitions as follows:
Please refer the attached project for setting the flag pin using assembly language. Here Flag pin 1 is set as output and high.
For more information, please refer to the "Flag I/O Register" and "GPIO Flags" sections available in the 'SHARC+ Core Programming Reference' manual linked below.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/sc58x-2158x-prm.pdf