Locale Icon
English
  • Forums

    Popular Forums

    • LTspice
    • Video
    • Power Management
    • RF & Microwave
    • Precision ADCs
    • FPGA Reference Designs

    Product Forums

    • Amplifiers
    • Clocks & Timers
    • Data Converters
    • Direct Digital Synthesis (DDS)
    • Energy
    • Interface and Isolation
    • MEMS Inertial Sensors
    • Power Management
    • Processors & DSP
    • Processors & Microcontrollers
    • Switches & Multiplexers
    • Sensors
    • Voltage References
    View All

    Application Forums

    • A2B Audio Bus
    • Audio
    • Automated Test Equipment (ATE)
    • Condition-Based Monitoring
    • Depth, Perception & Ranging Technologies
    • Embedded Vision Sensing Library
    • Motor Control Hardware Platforms
    • Precision Technology Signal Chains Library
    • Video
    • Wireless Sensor Networks Reference Library

    Design Center Forums

    • ACE Evaluation Software
    • ADEF System Platforms
    • Design Tools & Calculators
    • FPGA Reference Designs
    • Linux Software Drivers
    • Microcontroller no-OS Drivers
    • Power Studio Designer
    • Power Studio Planner
    • Reference Designs
    • Robot Operating System (ROS) SDK
    • Signal Chain Power (SCP)
    • Software Interface Tools
    • System Demonstration Platform (SDP) Support
  • Learn

    Highlighted Webinar

    Power Management Fundamentals II Session 4: Isolated Converters Explained

    What does isolation mean for power topologies? Let's review what galvanic isolation means and go through the terminology and standards. We'll explore isolation...

    Places

    • ADI Academy
    • ADI Webinars
    • Video Annex
    • Virtual Classroom

    Libraries

    • 3D ToF Depth Sensing Library
    • Continuous-Wave CMOS Time of Flight (TOF) Library
    • Embedded Vision Sensing Library
    • Gigabit Multimedia Serial Link (GMSL) Library
    • Optical Sensing Library
    • Precision Technology Signal Chains Library
    • Software Modules and SDKs Library
    • Supervisory Circuits Library
    • Wireless Sensor Networks Library

    Latest Webinars

    • Power Management Fundamentals II Session 6: Key Layout Considerations for Power
    • A 16T/16R X-Band Direct Sampling Phased Array Subsystem using Apollo MxFE
    • Power Management Fundamentals II Session 5: Deeper Look into Power Protection
    • Power Management Fundamentals II Session 4: Isolated Converters Explained
    • Maximize Your Power Regulator: Key Considerations for Thermal Performance
    View All Webinars
  • Community Hub

    Challenge Yourself!

      KCC's Quizzes AQQ296 about repairing an equation in a digital display

      1. Quote of this month: " When I die, I want to die like my grandfather who died peacefully in his sleep. Not screaming like all the passengers in his...

    View All

    What's Brewing

      Read a Blog, Take this Quiz for Another Chance to Win a Gift Card!

      Important: Read the blog first . The quiz questions are all based on the content from the blog: Too Much Chatter and Not Enough Talk - Learn the Benefits...

    View All

    Places

    • Community Help
    • Logic Lounge
    • Super User Program
    • Analog Dialogue Quiz

    Resources

    • EZ Code of Conduct
    • EZ How To Help Articles
    • Getting Started Guide
    • ADI: Words Matter
    • Community Help Videos
    View All
  • Blogs

    Highlighted Blogs

    ​​Functional Safety: A Driver of “Shift Left”​

    By Richard Obrien The key to faster, safer product development is to start smart - not catch up hard. In this blog, we’ll explore how the "Shift Left...

     

    The 5 Advantages of Hardware Fault Tolerance

    In IEC 61508, HFT stands for “ H ardware F ault T olerance”. HFT of one or higher means that there is no single fault that will cause a safety function...

    Latest Blogs

    • The Power Problem Inside Every AI Breakthrough: Part 1 of 3
    • Simplifying Stability with EVAL-KW4503Z: Part 1 of 3
    • Energy Transfer Considerations in Isolated SMPS: Part 2 of 4
    • Automating LTspice .NOISE Measurements with .STEP and .MEAS Directives: Part 2 of 3
    • ​​Channel Specification: The Key to GMSL Compliance​
    Read All Blogs

    ADI Blogs

    • EZ Spotlight
    • The Engineering Mind
  • ContentZone

    Visit ContentZone

    ContentZone

    Technical articles. Blogs. Videos. Your ADI content, all in one place.

    View ContentZone

    Featured Content

    Featured Content Title

    Blurb About Content

    View Content By Industry

    • Aerospace and Defense Systems
    • Automotive Solutions
    • Consumer Technology Solutions
    • Data Center Solutions
    • Energy Solutions
    • Healthcare Solutions
    • Industrial Automation Technology Solutions
    • Instrumentation and Measurement Solutions
    • Intelligent Building Solutions
    • Wireless Communication Solutions

    View Content By Technology

    • A2B Audio Bus
    • ADI OtoSense Predictive Maintenance Solutions
    • Dynamic Speaker Management
    • Gallium Nitride (GaN) Technology
    • Gigabit Multimedia Serial Link (GMSL)
    • Industrial Vision
    • Power Solutions
    • Precision Technology
    • RF
    • Sensor Interfaces
    • SmartMesh
EngineerZone
EngineerZone
ADSP-SC5xx/ADSP-215xx
  • Log In
  • User
  • Site
  • Search
OR
Ask a Question
ADSP-SC5xx/ADSP-215xx
  • Processors & DSP
  • SHARC Processors
  • ADSP-SC5xx/ADSP-215xx
  • Cancel
ADSP-SC5xx/ADSP-215xx
Documents SCB arbitration/priority scheme
  • Q&A
  • Files
  • Documents
  • Members
  • Tags
  • Cancel
  • +ADSP-SC57x/2157x: FAQ
  • +ADSP-SC58x: FAQ
  • +PMU registers: FAQ
  • +SC58x: FAQ
  • +SHARC+: FAQ
  • +TMU: FAQ
  • +215XX: FAQ
  • +ADC Control Module: FAQ
  • +ADSP-21584: FAQ
  • +ADSP-215xxl: FAQ
  • +ADSP-SC573: FAQ
  • +ADSP-SC5xx/215xx: FAQ
  • +ADSP-SC5xx: FAQ
  • +CCES default startup routine: FAQ
  • +EMAC: FAQ
  • +HADC: FAQ
  • +Hardware Counter based Loops: FAQ
  • +L1 block: FAQ
  • +Preload code customization: FAQ
  • +RDEN bit: FAQ
  • +RGMII/RMII: FAQ
  • +SHARC EE-377: FAQ
  • +Sharc SC584: FAQ
  • +SMMR using MDMA2: FAQ
  • +UCOS: FAQ
  • +USBCLKSEL in CGU_CLKOUT: FAQ
  • ADSP-21569 SPORT single-transmitter multi-receiver example
  • ADSP-SC584 SSL Booting via ROM API from the ARM Cortex A5 (core0), SHARC0 and SHARC1
  • +adsp-sc584: FAQ
  • ADSP-SC594 SPDIF Example
  • Are code segments placed in block1 and block2, when data caches are enabled?
  • ASRC TDM8/TDM16 Example for ADSP-SC59x
  • Can we use internal pull down resistor for ADSP-SC59x/ADSP-2159x LP_CLK and LP_ACK pins instead of external pull down?
  • +CDU: FAQ
  • Custom Error Handler in Booting for SC594
  • DAI Interrupt example for ADSP-SC573
  • Does QUAD SPI open-drain mode need external pull-up resistors for each of these signals (MISO, MOSI, D2 & D3) in ADSP-21569
  • Does the LRCLK support 50% duty cycle in TDM mode?
  • Does the TMREXP(Timer Expired) pin support in latest SHARC processor?
  • Driver file support for the ADSP-SC584/SC589 custom board, which utilizes the same flash and DDR as Ez-kit.
  • Flash write example for ADSP-SC573 Ez-Kit
  • How many cycles for a cache hit/miss?
  • How to configure DAI interrupt in ADSP-21569?
  • How to use Assembly to Control Core Flags?
  • How to use PCG trigger event
  • How to use PC_07 instead of SYS_FAULT in ADSP-2156x/ADSP-SC59x/ADSP-2159x ?
  • +IDLE: FAQ
  • Is it possible to change the sampling/driving edges of the ASRC?
  • Is it possible to configure the DSP as Master and Host as Slave once SPI slave booting done?
  • Is it possible to disable/halt/pause the SHARC0/SHARC1 cores from ARM core?
  • Is it possible to verify Secure Booting without programming Keys into OTP Memory?
  • Is the SPIx_RDY signal necessary for SPI slave boot?
  • JEDEC thermal Resistance Data estimation for "θJA, θJC, ΨJT" in ADSP-SC5xx/ADSP-215xx processor.
  • +Local Oscillator: FAQ
  • +MLB channels: FAQ
  • +MSI IDMAC: FAQ
  • +Program the CBS parameters: FAQ
  • +SC57x: FAQ
  • SCB arbitration/priority scheme
  • +Sign and encrypt a normal bootstream: FAQ
  • SPI example for ADSP-SC584
  • SPI secure slave boot
  • +SPORT with ACM: FAQ
  • +SWU: FAQ
  • Understanding Halt feature in ACM Mode
  • Usage of flush_data_buffer api
  • Using MCAPI/MDMA for ADSP-SC594 Dual-SHARC Audio Talkthrough
  • What is "Multiplexed Function Input Tap" available in the "Signal Multiplexing" table in the datasheet.
  • What is the clock configuration (HFCLK, BCLK) required to transmit SPDIF?
  • What is the difference between ENUM_DMA_CFG_XCNT_INT and ENUM_DMA_CFG_PERIPH_INT?
  • What is the SPORT Latency using DMA between the SHARC cores(Core1 & Core2) for ADSP-SC58x?
  • What is the supported SLCK0 divisor value for ADSP-2156x

SCB arbitration/priority scheme


Processor: ADSP-SC57x

The SCB bus arbitration mechanism ensures fair and efficient bus access based on predefined rules. Each slave interface in the system is assigned a configurable Quality of Service (QoS) value for its read and write channels, which determines the priority of its transactions when competing for bus access.

During arbitration, the system compares the QoS values of competing transactions, with higher QoS values receiving higher priority and being serviced first. If two transactions have the same QoS value, the Least Recently Granted (LRG) algorithm is applied to decide which transaction gains access, ensuring fairness and avoiding starvation.

Masters are organized into three priority groups: Group A (high priority), Group B (medium priority), and Group C (low priority). Within each group, if multiple masters have the same QoS value, they are treated equally in priority. If these masters attempt to access the bus at the same time, the LRG algorithm determines which one will proceed.

The QoS value for masters is programmable, but certain guidelines must be followed. For example, the highest QoS in a lower priority group (e.g., Group C) must be lower than the lowest QoS in the medium priority group (e.g., Group B), and the highest QoS in a medium priority group (e.g., Group B) must be lower than the lowest QoS in the higher priority group (e.g., Group A).

This arbitration mechanism ensures that masters from different priority groups are granted bus access in a predictable and fair manner, preventing any single master from monopolizing the bus and maintaining system balance.

  • Share
  • History
  • More
  • Cancel
analog-devices logo

About Analog Devices

  • Who We Are
  • Careers
  • Newsroom
  • What We Do (Signals+)
  • Investor RelationsExternalLink
  • Quality & Reliability
  • Sales and Distribution
  • What's New on Analog.com
  • Contact Us

Find Help

  • Support
  • Resources
  • WikiExternalLink
  • Analog Dialogue
  • ADI Developer PortalExternalLink

myAnalog

Interested in the latest news and articles about ADI products, design tools, training, and events?

Go to myAnalog
  • Instagram page
  • Twitter page
  • Linkedin page
  • Youtube page
  • Facebook
  • Legal and Risk
  • Accessibility
  • Privacy Policy
  • Privacy Settings
  • Cookie Settings

©2026 Analog Devices, Inc. All Rights Reserved

analog-devices

About Analog Devices

Down Up
  • Who We Are
  • Careers
  • Newsroom
  • What We Do (Signals+)
  • Investor RelationsExternalLink
  • Quality & Reliability
  • Sales and Distribution
  • What's New on Analog.com
  • Contact Us

Find Help

Down Up
  • Support
  • Resources
  • WikiExternalLink
  • Analog Dialogue
  • ADI Developer PortalExternalLink

myAnalog

Interested in the latest news and articles about ADI products, design tools, training, and events?

Go to myAnalog
Instagram page Facebook Twitter page Linkedin page Youtube page
  • Legal and Risk
  • Accessibility
  • Privacy Policy
  • Privacy Settings
  • Cookie Settings

©2026 Analog Devices, Inc. All Rights Reserved