Processor: ADSP-SC58x/ADSP-2158x
L1 instruction and data access types are spread over four stages of core pipeline: address preprocessing and conflict generation, address to memory block, data from memory block and data merging. L1 Cache operation has to fit within these four stages of core pipeline.
For cache hit, all the operations complete in four core clock cycles.
For cache miss, the fourth stage of the access takes multiple cycles.
For more information, please refer the Cache Miss Cases [Page No:268/798] and Cache miss [Page No:152/798] in PRM given below link,
https://www.analog.com/media/en/dsp-documentation/processor-manuals/sc58x-2158x-prm.pdf