The CGU_DIV.S0SEL selects the divisor in the SCLK0 equation: SCLK0 frequency = (SYSCLK frequency) / CGU_DIV.S0SEL
The setting on the register(CGU_DIV.S0SEL) is possible from 1 to 8, but is only 2, 4 or 6 only effective. The frequency ratios of SYSCLK to SCLK0 are 6:1, 4:1 or 2:1. The processor does not support any other frequency ratio.