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Processors and DSP
SHARC Processors
ADSP-SC5xx/ADSP-215xx
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ADSP-SC5xx/ADSP-215xx
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ADSP-SC58x/2158x PKTE Hashing-Decryption - Example code
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ADSP-SC57x/2157x: FAQ
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ADSP-SC58x: FAQ
ADSP-SC58x FMU(Fault Management Unit) Example Code.
ADSP-SC58x SPI Quad example code
ADSP-SC58X How to configure EMDMA Gather mode
ADSP-SC58x/2158x ACM- Example code
How to configure GIC of edge triggered interrupt sources?
ADSP-SC58x/2158x ASRC:Example codes
ADSP-SC58x/2158x Cortex A5 Software Interrupt- Example code
How to enable only L1 cache and not L2 cache OR vice-versa?
ADSP-SC58x/2158x Counter: Example code
How to extend number of channels in HADC
ADSP-SC58x/2158x DAI : What's new?
ADSP-SC58x/2158x interrupt SHARC core from ARM:Example code
How to select PSIZE and MSIZE fields of the MDMA configuration register on ADSP-SC58x/ADSP-2158x ?
ADSP-SC58x/2158x L2 access restriction from MDMA using SMPU - Example code
ADSP-SC58x/2158x Multicore: Example Code
ADSP-SC58x/2158x OTP General Purpose space programming- Example code
ADSP-SC58x/2158x PCG : Example codes
ADSP-SC58x/2158x PKA ECC multiplication - Example code
Is it possible to change the default boot mode peripheral instances?
ADSP-SC58x/2158x PKTE Encryption - Example code
Is it possible to run a DDR2 device at DCLK=400 MHz, CCLK=450 MHz, SYSCLK=225Mz on ADSP-SC58x/ADSP-2158x processors?
ADSP-SC58x/2158x PKTE Encryption-Hashing - Example code
Is it possible to run all the accelerators FIR/IIR/FFT in ADSP-SC58x/ADSP-2158x simultaneously?
ADSP-SC58x/2158x PKTE Hashing-Decryption - Example code
Is Secure booting supported in Open part in ADSP-SC58x?
ADSP-SC58x/2158x PWM: What's new?
ADSP-SC58x/2158x SPDIF-RX feature list: What's new?
ADSP-SC58x/2158x SPDIF: Example code
ADSP-SC58x/2158x SPI - Example Code
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ADSP-SC58x/2158x SPI XIP - Example code
ADSP-SC58x/2158x TRNG - Example code
ADSP-SC58x/2158x UART autobaud - Code Example
ADSP-SC58x/2158x Watchdog Timer:Example code
Is there a way to slow down the compute engine of the FFTA on ADSP-SC58x/ADSP-2158x processor?
ADSP-SC58x/ADSP-215xx SHARC+ Core Timer with Interrupt Example Code
Is there any L2 cache in ADSP-SC58x?
How can I validate the DDR interface on my newely designed board based on ADSP-SC58x/ADSP-2158x processors?
ADSP-SC5xx/ADSP-215xx - DDR memory Test
Is there any restriction on the types of memories supported by MDMA on ADSP-SC58x/ADSP-2158x?
How can the high speed FFTA DMA engine on ADSP-SC58x/ADSP-2158x be used in MDMA mode?
Highlights of MSI on ADSP-SC58x
Is there anything equivalent to External Port DMA (EPDMA) on ADSP-214xx processors available on ADSP-SC58x/ADSP-2158x processors?
How FIR accelerator on ADSP-SC58x/ADSP-2158x is different than the FIR accelerator on ADSP-214xx?
Is VFP and Neon available in ADSP-SC58x?
How FFT accelertor on ADSP-SC58x/ADSP-2158x can be programmed?
How many CRC blocks available on ADSP-SC58x/ADSP-2158x processor ?
How is SWU on SC58x different from that on BF60x processor?
How is the ACM on SC58x different from that on BF60x processor?
What should I do to SYS_CLKIN1 on SC58x, if I need only one CLKIN in my system
Can ARM Cortex A5 access SHARC core internal memory space in ADSP-SC58x?
Can FIR accelerator access both on chip and off chip memories on ADSP-SC58x/ADSP-2158x processor?
Secure Slave boot modes fails to boot even after programming the correct Public and Private key in the OTP space in ADSP-SC58x. What else is missing?
What are the major changes in the programming model of the IIR accelerator on ADSP-SC58x/ADSP-2158x as compared to ADSP-214xx processors?
What all Boot modes are supported in ADSP-SC58x?
What are the major differences in between the programming model of DDR3, DDR2, and LPDDR modes in the DMC controller of ADSP-SC58x/ADSP-2158x?
What are the major features of the CRC engine on ADSP-SC58x/ADSP-2158x processors?
what's new in the SPI peripheral of SC58x processor?
Can I connect DDR3 memory device on one DMC and DDR2 memory device on another DMC on ADSP-SC58x/ADSP-2158x?
Can I use the MLB Clock on SC58x to clock an external system?
What DDR3/DDR2/LPDDR device sizes are supported by the DMC controller on ADSP-SC58x/ADSP-2158x?
Can IIR accelerator access both on chip and off chip memories on ADSP-SC58x/ADSP-2158x?
Can Performance Monitor Unit be used to calculate cycle counts for SHARC core?
What is maximum speed of operation supported by Link Port in ADSP-SC58x?
Can the CRC engine on ADSP-SC58x/ADSP-2158x be used to calculate 16 bit CRC ?
What is Oscillator Watchdog?
Can the existing SHARC assembly codes be re-used as it is with SHARC+ Core?
Can we single-step over the IDLE instruction?
What is the maximum DMA throughput supported by L2CTL memory system on ADSP-SC58x/ADSP-2158x processors?
Do both the SHARC+ Cores in ADSP-SC58x/ADSP-215xx share the same L1 Memory?
What is the maximum processing speed supported by Cortex-A5 in ADSP-SC58x?
Does MDMA support descriptor based DMAs on ADSP-SC58x/ADSP-2158x?
What is the maximum speed supported by the MLB interface on SC58x?
FAQ: What is Multiprocessor Offset in ADSPSC58x/ADSP-215xx processors??
What is the minimum DCLK frequency supported for various DDR modes on ADSP-SC58x/ADSP-2158x?
I have configured my MDMA on ADSP-SC58x correctly, but still the MDMA transfer doesn't work as expected. Am I missing something?
How many MDMA streams are supported by ADSP-SC58x/ADSP-2158x processors and how much bandwidth they support?
What is the size if L1 cache supported by Cortex A5 in ADSP-SC58x?
FIRA/IIRA Performance on ADSP-SC58x/2158x and ADSP-SC57x/2157x Processors
How DMC/DDR controller in ADSP-SC58x/ADSP-2158x different than DDR2 controller on ADSP-2146x ?
I installed the IIR DMA interrupt handler on ADSP-SC58x, but still the interrupt doesn't occur, what I may be missing?
In ADSP-SC58x, can the ARM core access the SHARC+ Core's L1 Memory?
What are the important features of the L2 memory system on ADSP-SC58x/ADSP-2158x processors?
What are the major changes in the programming model of the FIR accelerator on ADSP-SC58x/ADSP-2158x as compared to ADSP-214xx processors?
How does the ECC error protection on L2 memory system works on ADSP-SC58x/ADSP-2158x processors?
How can I run the core clock at maximum of 450MHz and also source a 125MHz at the CLK07 for the EMAC TXCLK?
How does the memory refresh operation in L2CTL memory system works on ADSP-SC58x/ADSP-2158x processors?
How FFT accelerator (FFTA) on ADSP-SC58x/ADSP-2158x is different as compared to ADSP-214xx processors / What are the major features of FFTA on ADSP-SC58x/ADSP-2158x ?
How IIR accelerator on ADSP-SC58x/ADSP-2158x is different than the FIR accelerator on ADSP-214xx?
How is GP Timer in SC57x/2157x different from that of SC58x?
How is the MLB interface on SC58x different from previous SHARC processors?
How is the SPI peripheral different from the older SHARC processors?
How many DMC controllers are present in ADSP-SC58x/ADSP-2158x processors?
How many instances of EMAC are present in SC58x? How are they different?
How the FIR and IIR accelerators in ADSP-SC57x/2157x processors are different than in ADSP-SC58x/2158x processors
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PMU registers: FAQ
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SC58x: FAQ
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SHARC+: FAQ
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TMU: FAQ
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215XX: FAQ
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ADC Control Module: FAQ
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ADSP-21584: FAQ
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ADSP-215xxl: FAQ
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ADSP-SC573: FAQ
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ADSP-SC5xx/215xx: FAQ
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ADSP-SC5xx: FAQ
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CCES default startup routine: FAQ
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EMAC: FAQ
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HADC: FAQ
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Hardware Counter based Loops: FAQ
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L1 block: FAQ
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Preload code customization: FAQ
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RDEN bit: FAQ
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RGMII/RMII: FAQ
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SHARC EE-377: FAQ
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Sharc SC584: FAQ
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SMMR using MDMA2: FAQ
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UCOS: FAQ
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USBCLKSEL in CGU_CLKOUT: FAQ
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adsp-sc584: FAQ
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CDU: FAQ
FAQ: ADSP-SC584 SSL Booting via ROM API from the ARM Cortex A5 (core0), SHARC0 and SHARC1
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IDLE: FAQ
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Local Oscillator: FAQ
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MLB channels: FAQ
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MSI IDMAC: FAQ
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Program the CBS parameters: FAQ
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SC57x: FAQ
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Sign and encrypt a normal bootstream: FAQ
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SPORT with ACM: FAQ
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SWU: FAQ
Usage of flush_data_buffer api
ADSP-SC58x/2158x PKTE Hashing-Decryption - Example code
Attached code configures the PKTE module to do decryption and hashing operation in parallel.
PKTE_Hash_Decrypt_Core0.zip
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