ADSP-SC58x/2158x SPI - Example Code

m not concerned with that at the moment.  If I un-comment the for loop near the end of the function the SPI2 port does send the data.  I've got a 'scope probe on the SPI clock signal so I can see and count the clock pulses.
I've also been able to use the link-port to send data using DMA in this manner, so I'm not sure why the SPI2 port doesn't send here.

Any thought as to what I could be missing?

Thanks,
Matt

Here's my defines:

#define SPI2_EN 1
#define SPI2_TEN 1 // 1: Transmit channel Enable
#define SPI2_REN 0 // 1: Receive channel Enable

#define SPI2_TxDMA_EN 1
#define SPI2_RxDMA_EN 0

/*****************************************************************************************************************************
******************* macros related to SPI0 CONTROL REGISTER **************************
******************************************************************************************************************************/
#define SPI2_MSTR 1 // 0: Slave, 1: Master
#define SPI2_SIZE 0 // 0: 8-bit, 1: 16-bit, 2: 32-bit, 3: reserved
#define SPI2_CPHA 1 // 0: SCK toggles from middle of the first data bit
// 1: SCK toggles from beginning of the first data bit
#define SPI2_CPOL 0 // 0: Active low SCK, 1: Active high SCK
#define SPI2_ASSEL 1 // 0: SSEL controlled through SW, 1: SSEL controlled through HW
#define SPI2_SELST 0 // SSEL state between transfers
// 0: deasserted (high), 1: asserted (low) between transfers
#define SPI2_LSBF 0 // 0: MSB Tx/Rx first, 1: LSB Tx/Rx first
#define SPI2_EMISO 1 // applicable only when slave (in transmit mode)
// 0: Disable MISO pin, 1: Enable MISO pin.....
#define SPI2_PSSE 0 // Enable signaling of MODF error when configured as a master
#define SPI2_ODM 1 // Enable Open Drain Mode

#define SPI2_FCEN 0 // 1: Flow control enabled
#define SPI2_FCCH 0 // 0: Flow-control on RX FIFO, 1: Flow-control on Tx FIFO
#define SPI2_FCPL 0 // Active polarity of RDY signal: Active implies ready for transfer
// 0: Active low polarity, 1: Active high polarity
#define SPI2_FCWM 0 // Flow-control water-mark
// 0: TFIF0 empty or RFIFO full
// 1: TFIFO 75% or more empty or RFIFO 75% or more full
// 2: TFIFO 50% or more empty or RFIFO 50% or more full
#define SPI2_FMODE 0 // 1: Fast mode enable
#define SPI2_MIOM 0 // Multiple IO modes enable
// 0: Disable Multiple IO mode
// 1: Dual IO mode (DIOM)
// 2: Quad SPI mode (QSPI)
#define SPI2_SOSI 0 // Valid only in MIOM
// 0: start on MISO(in DOIM) or on SPIQ3 (in QSPI)
// 1: start on MOSI

/*****************************************************************************************************************************
******************* macros related to SPI0 TX CONTROL REGISTER **************************
******************************************************************************************************************************/
#define SPI2_TTI 1 // 1: Transmit Transfer Initiate
#define SPI2_TWCEN 1 // 1: Transmit word count Enable
#define SPI2_TDU 1 // 0: send last word on underrun, 1: send zero on underrun
#define SPI2_TDR 1 // Assert Transmit Data Request on following condition
// 0: Disabled
// 1: TFIFO not full
// 2: TFIFO 25% empty
// 3: TFIFO 50% empty
// 4: TFIFO 75% empty
// 5: TFIFO empty
#define SPI2_TRWM 3 // FIFO regular water-mark (condition to clear TUWM flag)
// 0: TFIFO full
// 1: TFIFO 25% empty
// 2: TFIFO 50% empty
// 3: TFIFO 75% empty
#define SPI2_TUWM 0 // FIFO urgent water-mark (condition to set TUWM flag and assert intr)
// 0: Disabled
// 1: TFIFO 25% empty
// 2: TFIFO 50% empty
// 3: TFIFO 75% empty
// 4: TFIFO empty

/*****************************************************************************************************************************
******************* macros related to SPI0 RX CONTROL REGISTER **************************
******************************************************************************************************************************/
#define SPI2_RTI 1 // 1: Receive Transfer Initiate
#define SPI2_RWCEN 1 // 1: Receive word count Enable
#define SPI2_RDO 0 // 0: Discard incoming data on overflow, 1: overwrite old data on overflow
#define SPI2_RDR 1 // Assert Receive Data Request on following condition
// 0: Disabled
// 1: RFIFO not empty
// 2: RFIFO 25% full
// 3: RFIFO 50% full
// 4: RFIFO 75% full
// 5: RFIFO full
#define SPI2_RRWM 3 // FIFO regular water-mark (condition to clear RUWM flag)
// 0: RFIFO empty
// 1: RFIFO 25% full
// 2: RFIFO 50% full
// 3: RFIFO 75% full
#define SPI2_RUWM 0 // FIFO urgent water-mark (condition to set RUWM flag and assert intr)
// 0: Disabled
// 1: RFIFO 25% full
// 2: RFIFO 50% full
// 3: RFIFO 75% full
// 4: RFIFO full

/*****************************************************************************************************************************
******************* macros related to SPI0 CLOCK and DELAY REGISTER **************************
******************************************************************************************************************************/

#define SPI2_BAUD 999 // [15:0] BAUD = [SCLK1/(SPI_clock)] - 1 ;
#define SPI2_STOP 1 // [ 7:0] Transfer delay time in multiples of SCK
#define SPI2_LEADx 1 // 1: Extended (1 SCK) LEAD control
#define SPI2_LAGx 1 // 1: Extended (1 SCK) LAG control

/*****************************************************************************************************************************
******************* macros related to SPI0 SSEL REGISTER **************************
******************************************************************************************************************************/

#define SPI2_SSE1 1 // 1: SPI_SSEL1 enable
#define SPI2_SSE2 0 // 1: SPI_SSEL2 enable, muxed with SPI0D3
#define SPI2_SSE3 0 // 1: SPI_SSEL3 enable, muxed with SPI0D2
#define SPI2_SSE4 0 // 1: SPI_SSEL4 enable
#define SPI2_SSE5 0 // 1: SPI_SSEL5 enable, muxed with SPI1_SSEL4
#define SPI2_SSE6 0 // 1: SPI_SSEL6 enable
#define SPI2_SSE7 0 // 1: SPI_SSEL7 enable

I've got a function to transmit the data like this:

DMA_Regs SPI2_DMA;

void spiDSP2DMA( MSGPIPE *msg, int nRet )
{
static int once = 1;

if( once )
{
*pREG_SPU0_SECUREP99 = BITM_SPU_SECUREP_MSEC | BITM_SPU_SECUREP_SSEC; // SPI2 security
*pREG_SPU0_SECUREP105 = BITM_SPU_SECUREP_MSEC | BITM_SPU_SECUREP_SSEC; // SPI2 security, Tx DMA
*pREG_SPU0_SECUREP106 = BITM_SPU_SECUREP_MSEC | BITM_SPU_SECUREP_SSEC; // SPI2 security, Rx DMA

*pREG_PORTE_DATA_SET = 0x08;
*pREG_PORTE_DIR_SET |= 0x08;

once = 0;
}

selectDSP2 // take the DSP2 ~SS line
*pREG_PORTE_DATA_CLR = 0x08; // create a trigger for debug via hardware

*pREG_SPI2_CLK = ((SPI2_BAUD << BITP_SPI_CLK_BAUD) & BITM_SPI_CLK_BAUD) ;

*pREG_SPI2_DLY = ( ((SPI2_STOP << BITP_SPI_DLY_STOP) & BITM_SPI_DLY_STOP) |
((SPI2_LEADx<< BITP_SPI_DLY_LEADX)& BITM_SPI_DLY_LEADX) |
((SPI2_LAGx << BITP_SPI_DLY_LAGX) & BITM_SPI_DLY_LAGX) );

*pREG_SPI2_CTL = ( ((SPI2_MSTR << BITP_SPI_CTL_MSTR) & BITM_SPI_CTL_MSTR) |
((SPI2_PSSE << BITP_SPI_CTL_PSSE) & BITM_SPI_CTL_PSSE) |
((SPI2_ODM << BITP_SPI_CTL_ODM) & BITM_SPI_CTL_ODM ) |
((SPI2_CPHA << BITP_SPI_CTL_CPHA) & BITM_SPI_CTL_CPHA) |
((SPI2_CPOL << BITP_SPI_CTL_CPOL) & BITM_SPI_CTL_CPOL) |
((SPI2_ASSEL<< BITP_SPI_CTL_ASSEL)& BITM_SPI_CTL_ASSEL) |
((SPI2_SELST<< BITP_SPI_CTL_SELST)& BITM_SPI_CTL_SELST) |
((SPI2_EMISO<< BITP_SPI_CTL_EMISO)& BITM_SPI_CTL_EMISO) |
((SPI2_SIZE << BITP_SPI_CTL_SIZE) & BITM_SPI_CTL_SIZE) |
((SPI2_LSBF << BITP_SPI_CTL_LSBF) & BITM_SPI_CTL_LSBF) |
((SPI2_FCEN << BITP_SPI_CTL_FCEN) & BITM_SPI_CTL_FCEN) |
((SPI2_FCCH << BITP_SPI_CTL_FCCH) & BITM_SPI_CTL_FCCH) |
((SPI2_FCPL << BITP_SPI_CTL_FCPL) & BITM_SPI_CTL_FCPL) |
((SPI2_FCWM << BITP_SPI_CTL_FCWM) & BITM_SPI_CTL_FCWM) |
((SPI2_FMODE<< BITP_SPI_CTL_FMODE)& BITM_SPI_CTL_FMODE) |
((SPI2_MIOM << BITP_SPI_CTL_MIOM) & BITM_SPI_CTL_MIOM) |
((SPI2_SOSI << BITP_SPI_CTL_SOSI) & BITM_SPI_CTL_SOSI) );

*pREG_SPI2_TXCTL = (((SPI2_TTI << BITP_SPI_TXCTL_TTI) & BITM_SPI_TXCTL_TTI) |
((SPI2_TWCEN<< BITP_SPI_TXCTL_TWCEN)& BITM_SPI_TXCTL_TWCEN) |
((SPI2_TDU << BITP_SPI_TXCTL_TDU) & BITM_SPI_TXCTL_TDU) |
((SPI2_TDR << BITP_SPI_TXCTL_TDR) & BITM_SPI_TXCTL_TDR) |
((SPI2_TRWM << BITP_SPI_TXCTL_TRWM) & BITM_SPI_TXCTL_TRWM) |
((SPI2_TUWM << BITP_SPI_TXCTL_TUWM) & BITM_SPI_TXCTL_TUWM) );

*pREG_SPI2_RXCTL = (((SPI2_RTI << BITP_SPI_RXCTL_RTI) & BITM_SPI_RXCTL_RTI) |
((SPI2_RWCEN<< BITP_SPI_RXCTL_RWCEN)& BITM_SPI_RXCTL_RWCEN) |
((SPI2_RDO << BITP_SPI_RXCTL_RDO) & BITM_SPI_RXCTL_RDO) |
((SPI2_RDR << BITP_SPI_RXCTL_RDR) & BITM_SPI_RXCTL_RDR) |
((SPI2_RRWM << BITP_SPI_RXCTL_RRWM) & BITM_SPI_RXCTL_RRWM) |
((SPI2_RUWM << BITP_SPI_RXCTL_RUWM) & BITM_SPI_RXCTL_RUWM) );

*pREG_SPI2_TWC = BUFF_SIZE2;
*pREG_SPI2_TWCR = 0;
*pREG_SPI2_RWC = BUFF_SIZE1;
*pREG_SPI2_RWCR = 0;

*pREG_SPI2_SLVSEL = ( ((SPI2_SSE1 << BITP_SPI_SLVSEL_SSE1) & BITM_SPI_SLVSEL_SSE1) |
((SPI2_SSE2 << BITP_SPI_SLVSEL_SSE2) & BITM_SPI_SLVSEL_SSE2) |
((SPI2_SSE3 << BITP_SPI_SLVSEL_SSE3) & BITM_SPI_SLVSEL_SSE3) |
((SPI2_SSE4 << BITP_SPI_SLVSEL_SSE4) & BITM_SPI_SLVSEL_SSE4) |
((SPI2_SSE5 << BITP_SPI_SLVSEL_SSE5) & BITM_SPI_SLVSEL_SSE5) |
((SPI2_SSE6 << BITP_SPI_SLVSEL_SSE6) & BITM_SPI_SLVSEL_SSE6) |
((SPI2_SSE7 << BITP_SPI_SLVSEL_SSE7) & BITM_SPI_SLVSEL_SSE7) );

*pREG_SPI2_SLVSEL |= ENUM_SPI_SLVSEL_SSEL1_HI ;

// *pREG_SPI2_IMSK_SET = BITM_SPI_IMSK_MF ;
// if (SPI2_REN)
// *pREG_SPI2_IMSK_SET |= (BITM_SPI_IMSK_RUWM | BITM_SPI_IMSK_ROR | BITM_SPI_IMSK_RS | BITM_SPI_IMSK_RF );
// if (SPI2_TEN)
// *pREG_SPI2_IMSK_SET |= (BITM_SPI_IMSK_TUWM | BITM_SPI_IMSK_TUR | BITM_SPI_IMSK_TC | BITM_SPI_IMSK_TS | BITM_SPI_IMSK_TF );

// SPI2.Tx_Done = !SPI2_TEN;
// SPI2.Rx_Done = !SPI2_REN;
//__builtin_ssync();

#if SPI2_SIZE == 0
SPI2_DMA.CFG = (ENUM_DMA_CFG_MSIZE01 | ENUM_DMA_CFG_PSIZE01 | ENUM_DMA_CFG_XCNT_INT | ENUM_DMA_CFG_STOP);
SPI2_DMA.XMOD= 1;
#elif SPI2_SIZE == 1
SPI2_DMA.CFG = (ENUM_DMA_CFG_MSIZE02 | ENUM_DMA_CFG_PSIZE02 | ENUM_DMA_CFG_XCNT_INT | ENUM_DMA_CFG_STOP);
SPI2_DMA.XMOD= 2;
#elif SPI2_SIZE == 2
SPI2_DMA.CFG = (ENUM_DMA_CFG_MSIZE04 | ENUM_DMA_CFG_PSIZE04 | ENUM_DMA_CFG_XCNT_INT | ENUM_DMA_CFG_STOP);
SPI2_DMA.XMOD= 4;
#endif

#if (SPI2_TEN & SPI2_TxDMA_EN)
*pREG_DMA26_CFG = ( ENUM_DMA_CFG_READ | SPI2_DMA.CFG);
*pREG_DMA26_XCNT = BUFF_SIZE2;
*pREG_DMA26_XMOD = SPI2_DMA.XMOD;
*pREG_DMA26_ADDRSTART= SPI2_Tx_BUFFER;
*pREG_DMA26_CFG |= ENUM_DMA_CFG_EN ;
//__builtin_ssync();
#endif
#if (SPI2_REN & SPI2_RxDMA_EN)
*pREG_DMA27_CFG = ( ENUM_DMA_CFG_WRITE | SPI2_DMA.CFG);
*pREG_DMA27_XCNT = BUFF_SIZE1;
*pREG_DMA27_XMOD = SPI2_DMA.XMOD;
*pREG_DMA27_ADDRSTART= SPI2_Rx_BUFFER;
*pREG_DMA27_CFG |= ENUM_DMA_CFG_EN ;
//__builtin_ssync();
#endif

*pREG_SPI2_TXCTL |= ((SPI2_TEN << BITP_SPI_TXCTL_TEN) & BITM_SPI_TXCTL_TEN);
*pREG_SPI2_RXCTL |= ((SPI2_REN << BITP_SPI_RXCTL_REN) & BITM_SPI_RXCTL_REN);
*pREG_SPI2_CTL |= ((SPI2_EN << BITP_SPI_CTL_EN) & BITM_SPI_CTL_EN);

// for( int i = 0; i < BUFF_SIZE2; i++ )
// {
// while( (*pREG_SPI2_STAT & BITM_SPI_STAT_TFS) == ENUM_SPI_STAT_TFIFO_FULL ); // wait if/while the TxFIFO is full
//
// *pREG_SPI2_TFIFO = ( uint32_t )SPI2_Tx_BUFFER[ i ]; // place outgoing data word in SPI TxFIFO
// }

// WAIT_FOR_REMOTE_DSP // wait for remote chip to set flag
releaseDSP2 // release the DSP2 ~SS line
*pREG_PORTE_DATA_SET = 0x08; // reset trigger for debug via hardware
}

I've taken out the interrupt mask setting, I'

I'm interested in using the SPI2 port to transmit using DMA.  I'm using your example as a guide.  As of now I haven't been able to get the DMA to send the data from memory to the SPI for transmit.

Hello,