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ADSP-SC5xx/ADSP-215xx
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Documents Code Example: Controller Area Network (CAN) for ADSP-SC573
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  • +ADSP-SC57x/2157x: FAQ
  • +ADSP-SC58x: FAQ
  • +PMU registers: FAQ
  • +SC58x: FAQ
  • +SHARC+: FAQ
  • +TMU: FAQ
  • +215XX: FAQ
  • +ADC Control Module: FAQ
  • +ADSP-21584: FAQ
  • +ADSP-215xxl: FAQ
  • -ADSP-SC573: FAQ
    • Code Example: Controller Area Network (CAN) for ADSP-SC573
  • +ADSP-SC5xx/215xx: FAQ
  • +ADSP-SC5xx: FAQ
  • +CCES default startup routine: FAQ
  • +EMAC: FAQ
  • +HADC: FAQ
  • +Hardware Counter based Loops: FAQ
  • +L1 block: FAQ
  • +Preload code customization: FAQ
  • +RDEN bit: FAQ
  • +RGMII/RMII: FAQ
  • +SHARC EE-377: FAQ
  • +Sharc SC584: FAQ
  • +SMMR using MDMA2: FAQ
  • +UCOS: FAQ
  • +USBCLKSEL in CGU_CLKOUT: FAQ
  • ADSP-21569 SPORT single-transmitter multi-receiver example
  • ADSP-SC584 SSL Booting via ROM API from the ARM Cortex A5 (core0), SHARC0 and SHARC1
  • +adsp-sc584: FAQ
  • ADSP-SC594 SPDIF Example
  • ADSP-SC835 SPI Slave transmitter and Master Receiver example code
  • Are code segments placed in block1 and block2, when data caches are enabled?
  • ASRC TDM8/TDM16 Example for ADSP-SC59x
  • Can we use internal pull down resistor for ADSP-SC59x/ADSP-2159x LP_CLK and LP_ACK pins instead of external pull down?
  • +CDU: FAQ
  • Custom Error Handler in Booting for SC594
  • DAI Interrupt example for ADSP-SC573
  • Do ADSP-SC58x/ADSP-SC57x support adi_pkte.h and adi_pka.h?
  • Does QUAD SPI open-drain mode need external pull-up resistors for each of these signals (MISO, MOSI, D2 & D3) in ADSP-21569
  • Does the LRCLK support 50% duty cycle in TDM mode?
  • Does the TMREXP(Timer Expired) pin support in latest SHARC processor?
  • Driver file support for the ADSP-SC584/SC589 custom board, which utilizes the same flash and DDR as Ez-kit.
  • Flash write example for ADSP-SC573 Ez-Kit
  • How many cycles for a cache hit/miss?
  • How many times the DAI can be routed using SRU?
  • How to configure DAI interrupt in ADSP-21569?
  • How to use Assembly to Control Core Flags?
  • How to use PCG trigger event
  • How to use PC_07 instead of SYS_FAULT in ADSP-2156x/ADSP-SC59x/ADSP-2159x ?
  • +IDLE: FAQ
  • Is it possible to change the sampling/driving edges of the ASRC?
  • Is it possible to configure the DSP as Master and Host as Slave once SPI slave booting done?
  • Is it possible to disable/halt/pause the SHARC0/SHARC1 cores from ARM core?
  • Is it possible to verify Secure Booting without programming Keys into OTP Memory?
  • Is the SPIx_RDY signal necessary for SPI slave boot?
  • JEDEC thermal Resistance Data estimation for "θJA, θJC, ΨJT" in ADSP-SC5xx/ADSP-215xx processor.
  • +Local Oscillator: FAQ
  • +MLB channels: FAQ
  • +MSI IDMAC: FAQ
  • Once the processor is locked, is it possible to debug or flash a new application?
  • +Program the CBS parameters: FAQ
  • +SC57x: FAQ
  • SCB arbitration/priority scheme
  • +Sign and encrypt a normal bootstream: FAQ
  • SPI example for ADSP-SC584
  • SPI secure slave boot
  • +SPORT with ACM: FAQ
  • +SWU: FAQ
  • Understanding Halt feature in ACM Mode
  • Usage of flush_data_buffer api
  • Using MCAPI/MDMA for ADSP-SC594 Dual-SHARC Audio Talkthrough
  • What is "Multiplexed Function Input Tap" available in the "Signal Multiplexing" table in the datasheet.
  • What is the clock configuration (HFCLK, BCLK) required to transmit SPDIF?
  • What is the difference between ENUM_DMA_CFG_XCNT_INT and ENUM_DMA_CFG_PERIPH_INT?
  • What is the recommended TMU_GAIN and TMU_OFFSET value for Calibration?
  • What is the SPORT Latency using DMA between the SHARC cores(Core1 & Core2) for ADSP-SC58x?
  • What is the supported SLCK0 divisor value for ADSP-2156x

Code Example: Controller Area Network (CAN) for ADSP-SC573

The ADSP-SC57x processor contains a Controller Area Network (CAN) module based on the CAN 2.0B (active) protocol. Attached are the code examples of CAN transmitter and Receiver for ADSP-SC573 Ez-Kit. I have used  extended (29-bit) identifiers for MailBox 10.

 

CAN0_TX_CAN1_RX.zip

CAN0_TX.zip

CAN1_RX.zip

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