Q&A - Recent Threads

Getting processed DMA buffer in SPORT group callback

Vetrivel — Sun, 15 Mar 2026 19:21:56 GMT

Hi Team,

This about how to get the processed SPORT DMA data buffer in group configuration.

The API adi_sport_GlobalRegisterCallback(), takes the callback function of type void (*ADI_CALLBACK)(void *pCBParam, uint32_t Event, void *pArg), where pArg points to the group handle.

In case of single SPORT config the call back function registered adi_sport_RegisterCallback() returns the processed buffer in pArg which is convinient. I understand it is not possible to pass the processed buffer in the group case as mutiple SPORTs are involved.

In our case, we have configured the multiple SPORT DMA with two DMA descriptors

ping ---> 0th index

pong ----> 1st index

in a circular configuration and grouped them together.

In the group callback, currently we are getting the completed buffer address from the SPORT_DMA_DSCPTR_PRV register of the specific SPORT, with the understanding that it points to the previous descriptor which is already processed by DMA

But the issue is sometimes during the very first interrupt, SPORT_DMA_DSCPTR_PRV points to pong buffer instead of ping.

1. Could you please explain the reason for such behaviour?

2. What is the recommeded way to get the processed buffer in the group callback case? Should we use a ping / pong flag to determine the buffer?

3. The internal struct in SPORT driver ADI_SPORT_GBL_GROUP has a member 'nBufferIndex' which could be helpful to determine the buffer. Is this exposed to user in any of the interface?

typedef volatile struct
{
  ADI_SPORT_HANDLE         *pDeviceArray;
  uint8_t             NoofDevices;
  bool                      bUsed;
  bool            bGblTrigEnable;
    ADI_CALLBACK              pfCallback;
    void                     *pCBParam;
    bool            bGroupInProgress;
    uint8_t           nBufferIndex;
    bool            bCircularBuff;
} ADI_SPORT_GBL_GROUP;

Thanks in advace.

Regards,

Vetrivel.

Does the SC587 support the adi_pkte.h and adi_pka.h drivers?

pwss — Fri, 13 Mar 2026 13:47:08 GMT

Does the SC587 support the adi_pkte.h and adi_pka.h drivers?

PKTE engine registers are readonly

BernhardM — Wed, 04 Mar 2026 08:52:47 GMT

Hi,

when using the PKTE Engine, writing the pREG_PKTE0_CDSC_CNT register, the failure "expression must be a modifiable lvalue" occures.

In ADSP_2156x_HPC_cdef.h the register is defined as const.

#define pREG_PKTE0_CDSC_CNT ((__I __C uint32_t *) REG_PKTE0_CDSC_CNT) /* Packet Engine Command Descriptor Count Register */

Same for the following registers:

#define pREG_PKTE0_INBUF_CNT ((__I __C uint32_t *) REG_PKTE0_INBUF_CNT) /* Packet Engine Input Buffer Count Register */

#define pREG_PKTE0_OUTBUF_CNT ((__I __C uint32_t *) REG_PKTE0_OUTBUF_CNT) /* Packet Engine Output Buffer Count Register */

Project is a c-project. (no cpp)

Regards

Bernhard

ADSP-SC572 TMU reading stuck at 127°C on custom board

lukar — Mon, 12 Jan 2026 18:00:20 GMT

Hello everyone,

We are trying to read the die temperature using the TMU on a custom board based on the ADSP-SC572. Our hardware design for the HADC/TMU block should be identical to the ADSP-SC573 EZ-KIT.

The main differences between the two boards are that in the number of cores and we have one clock source only on SYSCLKIN0, while the EZKIT has on both clock inputs.

To test the functionality, we are using the CCES example project "ReadTemperature_SC573_Cortex" (built for SC572 too).

On the EZ-KIT, the code works as expected, returning a stable value around 37°C.
On our custom SC572 board, the same code consistently returns exactly 127°C.

Does anyone have any suggestions as to why the TMU keeps reading 127 on the custom board? Could this be related to a specific HADC initialization or a hardware difference we might have overlooked?

I can provide schematics if needed.

Thanks in advance for your help!

UART DMA IDLE Detection

EricSa — Fri, 19 Dec 2025 11:10:28 GMT

Hey together,

I have a question regarding the UART RX on the ADSP-21569. I managed to build a continous DMA receiver by using 2 descriptors pointing circular to each other, thats perfect. The size of the buffers are 32 byte. So this means I always get an callback when i received 32 bytes via UART. But what happens when I only receive 31 bytes for whatever reason. I will not get any callback and the data stays in the buffer forever. Is there a way to detect, for example after 100ms, that there is data in the buffer and to read it out?

On some know MCUs this is done via the UART IDLE detection. Meaning when there is silence for more that 1 byte on the bus the UART IDLE interrupt is triggered and the data can be flushed from the DMA. I cant find any information about the IDLE interrupt but maybe there is a way to do it via polling, every 100ms or so.

Best regards,

Eric

detailed documentation for adi_rom_otp_get() function

dbray — Fri, 14 Nov 2025 21:01:40 GMT

Hello Forum,

With regard to the adi_rom_otp_get() function, would there be any information available to address any of the following questions?

1. The function returns 'false' for an unsuccesful read. Under what circumstances is 'false' returned? for example, when OTP is corrupted?

2. in the case that 'false' _is_ returned, are there any guidelines to show how application code should handle this case? e.g. retry? reboot?

3. what headers should be #included when compiling?

4. are there any reference code examples?

In my case, i am developing for the ADSP-594W. There is documentation in the ADSP-SC594W datasheet for adi_rom_otp_get(), but it does not quite cover the topics above.

Thank you

Combining "initcode" within SSL (Secure Boot Stream)

3lions — Thu, 09 Oct 2025 15:04:08 GMT

Our software implementation currently consists of an SSL/bootloader and "main" application. We wish to use a Secure Boot Stream to secure both the application and the SSL.

Our SSL .ldr file includes the initcode that's used to initialize DDR3, clocks etc. However, when using a Secure Boot Stream the bootrom fails to load the SSL because it includes the initcode block (this behavior is documented in EE-366).

Therefore, I believe we have to:

Run the SSL has to run in onboard L2 memory (since the L3/DDR is not yet initialized)
Import the "initcode" routines into the SSL, and execute them at startup.

I've implemented the above, using a custom linker script derived from the project provided here, however the main application doesn't boot.

I think the problem is that, since we're executing in L2 memory (the SSL is large, ~200K) this conflicts overlaps with the L2 memory that's reserved for the primary application.

Please can you confirm that aby L2 memory used by the SSL cannot be "reused" by the main application? If so, then do you have any other suggestions for how we can perform the "init" functionality within a Secure Boot Stream SSL?

Many thanks in advance.

How to get a frame sync interrupt?

pderocco — Tue, 16 Sep 2025 21:18:42 GMT

I have several SPORTs which are sharing a common bit clock and frame sync. I need to do I/O at the sample rate in an interrupt handler. Given that I have three input streams and two output streams, and it takes two interrupts per stereo sample, that's 10 interrupts per sample. Given the staggering interrupt overhead on a SHARC, even at 16KHz, that takes pretty much all the CPU time. So my idea is to use a single interrupt triggered by the frame sync via the DAI, in which I do two reads from each Rx register and two writes to each Tx register. I can use the ADI library to configure the SPORTs, and I'm writing registers directly to route the clocks and audio, but I'm having trouble configuring the interrupt. I don't see a DAI service or driver in the library for this part, so what do I need to do to get an interrupt on a particular edge of the common frame sync? Are there lower-level functions that I can use?

What I've tried so far is to write registers to route one of the SPORT's frame sync to the DAI misc interrupt 0, to assign that to the high-priority DAI interrupt to the SEC, and use adi_int_InstallHandler() to register my handler to interrupt 40, which is the high-priority DAI interrupt on this part. The SEC0_SCTL40 register shows CTG, SEN, and IEN equal to 1, but the SEC0_SSTAT40 register is zero. The DAI0 registers look reasonable except that the DAI0_IRPT_H register is always EEEEEEEE, which smells like it might be unreadable. No interrupts are happening, so I must be missing something. I'd rather do this through library calls instead of poking registers.

EMAC descriptor or buffer data flush.

Mothilal — Fri, 01 Aug 2025 09:11:46 GMT

H sir/Madam,

I am using SC594 SOM module with EV-SOMCRR-EZKIT board, trying to implement to read and write operation with EMACPhyLoopback.

after reading old data i want to flush descriptor and buffer data ( emac_data_tx.data or emac_data_rx & emac_desc_rx[desc_cnt].Buffer1, emac_desc_tx[desc_cnt].Buffer1).

can you please let me know how to reset the buffers and descriptor.

Regards

Mothilal.

I want to know how to deal with crashes that occur in C language and assembler.

mako2771 — Thu, 31 Jul 2025 04:53:50 GMT

Hi.

I am writing control in C language and filter calculations in assembler for high-speed calculations.
The input consists of two different sampling signals.
Signal acquisition uses DMA interrupts, and calculations use software interrupts. Additionally, I read and write to QSPI memory while outputting signals.
Switching soft interrupts or accessing memory causes a few lines of assembly code to break and crash the system. Alternatively, crashes occur due to issues with return address or jump address.
I understand that I should not use i6/i7/m7, etc., within assembly code, but
1: What other registers besides MODE1/ASTATX/CMMR0 should be saved within assembly code?
　2: I think there are registers that should be saved during interrupts. Which registers specifically?
How should this be written in C language? How should MODE1 be written?
The CMMR SYSCTL can be written as follows:
ESC_SYSCTL=*pREG_CMMR0_SYSCTL;

Thanks, Regards,

YAMAMOTO

GPI interrupt on both edges, PINT and related.

SpoonMan999 — Tue, 15 Jul 2025 15:41:51 GMT

Hello, I'm really, really confused about how GPIO pins, PINT and SEC are intended to be used in combination to generate user-defined interrupts for different events (level, edges), ports and pins.

The first headache came when I tried to understand the mapping of the ports/pins on the PINTs:

As far as I can understand from the above diagram:

PINT0 can generate interrupts for pins on PORT A and B, PINT1 can generate interrupts for pins on PORT B and C, while PINT2 can only generate interrupts for pins on PORT C.
Individually for each pin configured in each PINT, we can decide to which port the pin belongs to (e.g. for PINT0 we can configure if a pin belongs to port A or port B) and to which event we would like to be sensitive to (i.e. high level, low level, rising edge or falling edge).

The second headache came later when trying to enable an interrupt on both rising and falling edges on the same pin using the same PINT, which I solved in a completely fortuitous way by searching for help on Google and finding this link:

Single interrupt block for both rising and falling edges in ADSP-21569 - Documents - CrossCore Embedded Studio and Add-ins - EngineerZone

in which PC07 and PC23 (????) are successfully used to setup rising-edge and falling-edge interrupts, respectively, using PINT1 on the same physical pin PC07, calling adi_gpio_RegisterCallback() two times for setting up the same callback on both events.... and the following points remained to be clarified:

each PINT (0, 1, 2) can generate one IRQ (and only one) for each pin mapped, so even if ADI_GPIO_RESULT adi_gpio_RegisterCallback(ADI_GPIO_PIN_INTERRUPT const ePinInt,
uint32_t const Pins, ADI_GPIO_CALLBACK const pfCallback, void * const pCBParam) function gives the impression that we can install a different callback on different pins belonging to the same PINT, this is just a "software illusion" and we never need to install more than 3 callbacks (one per each PINT block) to handle all the interrupts in this world.... am I right?
since physical GPIO pins on all ports are numbered from 0 to 15, what are the pins numbered from 16 to 31 appearing in adi_gpio.h (see screenshot below)? Looks like they're the equivalent of pins 0-15 but left-shifted by 16 bits for the sole purpose of addressing upper BYTE2 and BYTE3 part of registers like REG_PINT0_INV_CLR when passing "pins" parameter to functions like adi_gpio_PinInt()? If so, why does everything have to be so complicated and counterintuitive?

How to transfer clock and data from DAI0 to DAI1?

Boschliu — Fri, 13 Jun 2025 07:49:42 GMT

Hi ,
As shown in the figure below, the TDM port on the SOC side has 6 PINs connected to DAI0. DAI0 receives clock and data, which are then transmitted to DAI1 through ADSP. DAI1 is connected to the 6 PINs of the A2B chip;

We expect to be able to transfer the clock and data from TDM to A2B, but from the actual SRU operation, it is not possible to transfer DAI0 to DAI1 because DAI0 can only provide to SPORT0~3, and DAI1 can only provide to SPORT4~7,
1. How to transfer clock and data from DAI0 to DAI1?
2. I tried using the following plan, but I have three questions
a. Is this data transmission mode reasonable??
b. Isn't the clock synchronization between DAI0 and DAI1 in this way??
c. Transferring sport0 to sport4: Transferring through adi_Sport_SMATransfer???

/*TDM to A2B*/

SRU(DAI0_PB01_O, SPT0_ACLK_I); /*DAI0 clock to SPORT 0A*/

SRU(DAI0_PB02_O, SPT0_AFS_I); /*DAI0 FS to SPORT 0A*/

SRU(DAI0_PB05_O, SPT0_AD0_I); /*DAI0 Data to SPORT 0A*/

//SRU(DAI0_PB06_O, SPT0_AD0_I); /*DAI0 Data to SPORT 0A*/

SRU2(SPT4_ACLK_O, DAI1_PB01_I); /*SPORT 4A clock to DAI1*/

SRU2(SPT4_AFS_O, DAI1_PB02_I); /*SPORT 4A FS to DAI1*/

SRU2(SPT4_AD0_O, DAI1_PB05_I); /*DAI0 Data to SPORT 0A*/

SRU(LOW, DAI0_PBEN01_I);

SRU(LOW, DAI0_PBEN02_I);

SRU(LOW, DAI0_PBEN05_I);

SRU2(HIGH, DAI1_PBEN01_I);

SRU2(HIGH, DAI1_PBEN02_I);

SRU2(HIGH, DAI1_PBEN05_I);

3. Refer to the CRS method in the manual to implement DAI0 to DAI1. There are some questions about these interfaces:
a. Only pins PB03~PB06 correspond to each other?
b. Our hardware PIN angle has been designed according to the schematic above. Can we continue to use this solution?

Shared Clock:

DAI0_CRS_PB03_O è DAI1_CRS_PB03_O

DAI0_CRS_PB05_O è DAI1_CRS_PB05_O

Frame Sync:

DAI0_CRS_PB04_O è DAI1_CRS_PB04_O

DAI0_CRS_PB06_O è DAI1_CRS_PB06_O

Shared Pin Buffer:

DAI0_CRS_PIN03 à DAI1_CRS_PIN03

DAI0_CRS_PIN05 à DAI1_CRS_PIN05

DAI0_CRS_PIN04 à DAI1_CRS_PIN04

DAI0_CRS_PIN06 à DAI1_CRS_PIN06

Thanks

What is the procedure for restarting the three cores of SC587 in the application context?

pwss — Fri, 23 May 2025 03:44:27 GMT

What is the procedure for restarting the three cores of SC587 in the application context?

Issue with SHARC Core1 Not Starting After Flash Programming ADSP-SC589-MINI

avfp — Fri, 09 May 2025 12:31:09 GMT

Hi everyone!

I created a multi-core project where:

Core0 (ARM) blinks LED12.
Core1 (SHARC) turns on LED10.

I followed this guide from Analog Devices to load the program into flash:
🔗 https://wiki.analog.com/resources/tools-software/crosscore/cces/getting-started/app

After flashing and restarting the board, only the ARM core is running as expected (LED12 is blinking). However, the LED10 controlled by the SHARC core does not turn on.

My question is about how the SHARC cores initialize:

Do SHARC cores have some kind of startup/init code?
How do they know where to find their program in flash and how to load it into SRAM?
Is there a specific setting I need to configure so that Core1 starts correctly along with Core0?

I've attached my project for reference. Any help or guidance would be greatly appreciated!

Best regards,
Thanks in advance for any support!

BLp_Secure_Boot_Stream.ldr generated using signtool-type BLp

pwss — Sun, 27 Apr 2025 08:14:21 GMT

What is the content format of the BLp_Secure_Boot_Stream.ldr binary signature file generated using “signtool -type BLp”?

I want to perform the signature verification operation of the BLp_Secure_Boot_Stream.ldr file in the application program, but I don't know how to calculate its HASH value?

PKTE: Is it possible to calculate an HMAC across multiple iterations?

3lions — Wed, 09 Apr 2025 21:07:53 GMT

Following up from my question here: PKTE decryption examples

The PKTE peripheral is capable of calculating hash across a large set of data by iterating over the input multiple times (which allows the processing of input data that exceeds the TOTLEN limit of 1MB). Similarly, it is able to perform a combined SHA hash/decrypt operation over multiple iterations.

HMAC is a lot trickier. Although I'm able to use the PKTE to calculate the HMAC on a single iteration (small data object), I have been unable to do the same across multiple iterations with chunks of input data. I'm looking for guidance on whether the PKTE is able to do this, and if so, what steps I'm missing.

As posted in my previous question, below is the Blackfin diagram (ee-368.pdf) that allowed me to calculate the HMAC. Basically, the outer and inner pad values are calculated as a "pre-process", and stored in the SA record which is then used for a single "final" hash calculation.

But how do we iterate over this? I have experimented with repeatedly issue the last step, saving the "hash_final" for last, but the computed value is incorrect. I'm not sure if it's possible, and if it is, what the inputs should be for the intermediate steps.

The document also shows a more convoluted process (method 2, below), but it's very unclear how this could be implemented, and there is no example code for this method:

Please can you offer some guidance on this? The HWRM is severely lacking in details on HMAC operation.

PKTE decryption examples

3lions — Thu, 20 Mar 2025 19:01:05 GMT

Hi there,

I'm attempting to use the PTKE module to decrypt a file. I was able to port the following example code from the SC8xx to SC573 and get it somewhat working:

ADSP-SC58x/2158x PKTE Hashing-Decryption - Example code

The challenge is that the example only deals with a single block (16 bytes) of data. When I attempt to decrypt a larger data object, only the first sixteen bytes are decrypted correctly. This applies to the Host, TCM and Autonomous modes, and I suspect it relates to the Initialization Vector, but it's difficult to know for sure.

The example code isn't very clear (mysterious, hardcoded values and commented out lines of code. This is a very complex peripheral, and it would help greatly if an example could be provided that is able to decrypt more data, say 1MB.

Thanks in advance.

I need a faster 40-bit & 64-bit IIR filter.

mako2771 — Wed, 05 Mar 2025 07:30:22 GMT

Hi.

I am building a filter with 80 2nd order IIR filters connected in series.
It processes 2 channel signals.
If I change from 21489 (450MHz) to 21565 (1000MHz), the processing time is the same.
I think it is stalled, but it was not same as EE375.
　f12 = f0*f4, f8 = f8+f12, f0 = dm(i2,m2), f4 = 　　　　
　pm(i9,m9); // 1-cycle SHARC+ stall
I don't know what to do to make it faster.
Please teach me.
The following program is the same as 21489.
What is causing the stall?
Also, please guide me on the 64-bit floating point filter as well.
The 64-bit is SIMD to calculate 2 channels at the same time to save time.

40bit------------------

lcntr=16 , do LOOPG until lce; // FILTER ---------------------------
f4=dm(i3,m1), f1=pm(i10,m9); // f1=Lx1(n) f4=Lb10
f8 =f1*f4, f4=dm(i3,m4), f2=pm(i10,m9); // f8=Lx1(n)*Lb10 f2=Rx1(n) f4=Rb10
lcntr=80 , do _loop_g until lce;
f9 =f2*f4, f4=dm(i3,m1), f0=pm(i12,m9); // f9=Rx1(n)*Rb10 f4=Lb11, Lx1(n-1)->f0
f12=f0*f4, f4=dm(i3,m4), f0=pm(i12,m9); // f12=Lx1(n-1)*Lb11 f4=Rb11, Rx1(n-1)->f0
f13=f0*f4, f8=f8+f12, f4=dm(i3,m1), f0=pm(i12,m9); // f13=Rx1(n-1)*Rb11 f8=sigmaL f4=Lb12, Lx1(n-2)->f0
f12=f0*f4, f9=f9+f13, f4=dm(i3,m0), f0=pm(i12,m9); // f12=Lx1(n-2)*Lb12 f9=sigmaR f4=Rb12, Rx1(n-2)->f0
f13=f0*f4, f8=f8+f12, f4=dm(i3,m1), f0=pm(i12,m9); // f13=Rx1(n-1)*Rb12 f8=sigmaL f4=La11, Ly1(n-1)->f0
f12=f0*f4, f9=f9+f13, f4=dm(i3,m4), f0=pm(i12,m9); // f12=Ly1(n-1)*La11 f9=sigmaR f4=Ra11, Ry1(n-1)->f0
f13=f0*f4, f8=f8+f12, f4=dm(i3,m1), f0=pm(i12,m9); // f13=Ry1(n-1)*Ra11 f8=sigmaL f4=La12, Ly1(n-2)->f0
f12=f0*f4, f9=f9+f13, f4=dm(i3,m0), f0=pm(i12,m12); // f12=Ly1(n-2)*La12 f9=sigmaR f4=Ra12, Ry1(n-2)->f0
f13=f0*f4, f1=f8+f12, f4=dm(i3,m1), pm(i12,m9)=f1; // f13=Ry1(n-2)*Ra12 f1=Ly1(n) f4=Lb20 f1->Lx1(n)
_loop_g: f8=f1*f4,f2=f9+f13,f4=dm(i3,m4), pm(i12,m11)=f2; // f8=Lx2(n)*Lb20 f2=Ry1(n) f4=Rb20 f2->Rx1(n)
f15=dm(i3,m2), f14=pm(i12,m10); // NextP coef NextP LYn(n)
dm(i2,m1)=f1, pm(i12,m9)=f1; // f1->Lyn(n)
LOOPG: dm(i2,m1)=f2, pm(i12,m11)=f2; // f2->Ryn(n)
dm(_IXgDLY40)=i12; // INDEX z-1

64bit--------------------------------------------------------------------------

f0=dm(i3,m1); // f0=inL(n)
lcntr=16 , do LOOPG until lce; // FILTER ---------------------------
s0=dm(i3,m1); // s0=inR(n)
r4=dm(i4,m2); // r4:s4=Lb10_l:Rb10_l f0=inL(n)
f3:2=cvt f0, r5=dm(i4,m2); // 40to64bit r5:s5=Lb10_h:Rb10_h f3:s3:inp(n)_h f2:s2=inp(n)_l
lcntr=80 , do _loop_g until lce;
f9:8=f3:2*f5:4, r4=dm(i4,m2), r0=pm(i12,m10); // f9:8=L:R(n)*L:Rb10_l r4:s4=Lb11_l:Rb11_l r0:s0~L:R_lx(n-1)
r5=dm(i4,m2), r1=pm(i12,m10); // r5:s5=Lb11_h:Rb11_h r1:s1=L:R_hx(n-1)
f13:12=f1:0*f5:4, r4=dm(i4,m2), r0=pm(i12,m10); // f13:12=L:Rx(n-1)*L:Rb11 r4:s4=b12_l r0=x(n-2)_l
f9:8=f9:8+f13:12, r5=dm(i4,m2), r1=pm(i12,m10); // sigma r5:s5=b12_h r1=x(n-2)_h
f13:12=f1:0*f5:4, r4=dm(i4,m2), r0=pm(i12,m10); // f13:12=L:Rx(n-2)*L:Rb12 r4:s4=a11_l r0=y(n-1)_l
f9:8=f9:8+f13:12, r5=dm(i4,m2), r1=pm(i12,m10); // sigma r5:s5=a11_h r1=y(n-1)_h
f13:12=f1:0*f5:4, r4=dm(i4,m2), r0=pm(i12,m10); // f13:12=L:Ry(n-1)*L:Ra11 r4:s4=a12_l r0=y(n-2)_l
f9:8=f9:8+f13:12, r5=dm(i4,m2), r1=pm(i12,m8); // sigma r5:s5=a12_h r1=y(n-2)_h
f13:12=f1:0*f5:4, r4=dm(i4,m2), pm(i12,m10)=r2; // f13:12=L:Ry(n-2)*L:Ra12 r4:s4=b20_l f2: -> x1_l(n)=y(n)
_loop_g: f3:2=f9:8+f13:12, r5=dm(i4,m2), pm(i12,m9)=r3; // sigma r5:s5=b20_h f3: -> x1_h(n)
f7=cvt f3:2, r6=dm(i4,m3), r10=pm(i12,m11); // 64to40bit y(n) NextP i4 NextP i12
f0=dm(i3,m1), pm(i12,m10)=r2; // f0=inL(n) SAVE y(n)_l
dm(i2,m1)=f7, pm(i12,m9)=r3; // Lch:y(n)->DATA40 SAVE y(n)_h
LOOPG: dm(i2,m1)=s7; // Rch:y(n)->DATA40
bit clr mode1 BITM_REGF_MODE1_PEYEN; //////////// SISD//////////////
m9=1;
dm(_IXDLY64)=i12; // INDEX z-1

Thanks, YAMAMOTO

ADSP-SC573 EZ-Kit Fails to Boot from External Flash, Enters Fault State on Restart

hisham — Fri, 31 Jan 2025 12:57:57 GMT

I am facing an issue with my ADSP-SC573 EZ-Kit where the board fails to boot from the external flash (W25Q128FV) and enters a fault state upon restart. Below are the details of the issue and the steps I have taken so far:

Issue Description:

Boot Failure: The board does not boot from the external flash after a restart. It enters a fault state, and the firmware does not load.
Firmware Programming: I am able to successfully program the external flash using the cldp tool (CrossCore Embedded Studio Device Programmer). The programming process completes without errors.
Debugging: I can debug the firmware in CrossCore Embedded Studio (CCES) without issues. The firmware runs correctly when loaded via the debugger.
Fault State: Upon restarting the board (without the debugger connected), the board does not boot and remains in a fault state.

Steps Taken So Far:

1. Flash Erase and Reprogram:

I have erased the entire 16MB external flash using the cldp command.

while verifying the flash program with the command:

cldp -proc ADSP-SC573 -emu ICE-1000 -core 1 -driver "C:\Analog Devices\ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2\ADSP-SC5xx_EZ-KIT\Examples\Device_Programmer\sc573\sharc\sc573_w25q128fv_dpia_Core1\sc573_w25q128fv_dpia_Core1.dxe" -cmd prog v -erase all -file Test_Core0.ldr -format bin

It gives the following error: Error: could not write file, load will not complete.

But with -cmd prog it completes loading the file without any errors.

2. Boot Mode Configuration:

The boot mode pins on the ADSP-SC573 are configured to boot from external flash (W25Q128FV).
Double-checked the hardware connections and confirmed that the boot mode settings are correct

Questions:

What could be causing the board to enter a fault state when booting from the external flash?
Are there any specific configurations or settings I need to check for booting from the W25Q128FV flash?
How can I debug the boot process to identify where it is failing?
Are there any known issues or workarounds related to booting from external flash on the ADSP-SC573?

Clock Generation Unit (CGU)

HiteshK — Wed, 22 Jan 2025 08:41:55 GMT

Where to find the highlighted bits..? How to activate these bits...?

Could you please share a template to configure CGU and CDU..(both assembly and C)?

How to playback a sound data saved as file on the ADZS-21489 EZ-Kit board?

CommunityWillDisplay — Fri, 15 Nov 2024 02:40:18 GMT

Hello.

I'm using the ADSP-21489 EZ-Kit board.

there is a sound source file, and i want to store it in the chip and play it when i need.

Is the ADSP-21489 support to do this?

Let me know any information or examples for solving such questions please.

Thanks.

Need help for the ATMOS lib to decode stream from HDMI chip

PowerPan — Sun, 03 Nov 2024 14:42:29 GMT

we have a problem while trying to decode ATMOS using your library for atmos. and our engineer has no clue what is the format of the de-mux audio stream, so just need your guide telling how to step-by-step to solve the problem. I have attached questions below, look forward to your kind reply

1. for the HDMI decoder de-mux the audio stream and output from 4 wires of data, so how could we know the audio format, and where could we find the audio format information from the stream? the document refers to IEC51937 and IEC60958 for more information, but we have no clue where to find the related part that describes details.

2. as I know, the library is written by Dolby, but before decoding, we need to tell the decoder library what format it should use, so, could you tell us which function could find out the format detail? or any demo de-mux stream for us to test?

Best regards,

Power Pan

uart dma stops sending data

captaanEletro — Sat, 26 Oct 2024 14:14:08 GMT

Hi team,

in adsp sharc 21583 , with cross core embedded studio 2.11.0.

i have 1ms ISR where the buffer tx_msg_buffer is filled and the Message_length is total number of bytes filled in the tx_msg_buffer.

the Baud rate is 460800.

Message length will be 36 bytes.

Issue:

the uart is to be used in DMA mode. but after few bytes of data transmission the data stops coming on UART. the code is running (verified by stopping the execution and checking the buffer). the buffer will contain data but, the data won't come on terminal
the core clock is 450 MHz, and SCLK_0 is 112.5MHz, At 921600 baud rate the data gets corrupted. HRM mentions that it supports the baud rate, but the data does not come correct. the bytes will be wrong. So, I had to use 460800 baud.

please suggest what is going wrong.

void WriteUartDsp (volatile unsigned char* tx_msg_buffer)
{




	/* Loop in while until the previous transmission is completed  */
	while (M_TRUE)
	{
		test = 0;
		test = *pREG_DMA20_STAT;

		/* Check the DMA status, if DMA status is Idle/Stop break the while loop*/
		if (M_ZERO == (test & M_DMA_RUN_STOP))
		{
			break;
		}

	}
	
	*pREG_SPU0_SECUREP82 =0x3; //uart rx dma 20
	*pREG_SPU0_SECUREP83 =0x3; //uart tx dma 21
	
	/* Set the UART0 Interrupt mask to zero*/
	*pREG_UART0_IMSK_SET = M_ZERO;

	/* Wait till the UART0 transmit hold and shift register are empty */
	while (M_ZERO == (*pREG_UART0_STAT & BITM_UART_STAT_TEMT))
	;
	while (M_ZERO == (*pREG_UART0_STAT & ENUM_UART_STAT_THR_EMPTY))
	;


	/* Disable the DMA 20 */
	*pREG_DMA20_CFG = ENUM_DMA_CFG_DIS;

	/* Assign the DMA start address for transmission */
	*pREG_DMA20_ADDRSTART = (void *) (M_MP_OFFSET | (T_U32) tx_msg_buffer);

	/*
	 * Configure DMA0 Registers, set STOP mode flow control, memory and
	 * physical transfer as 1 byte
	 */

	*pREG_DMA20_CFG = ( ENUM_DMA_CFG_MSIZE01 |
	ENUM_DMA_CFG_MSIZE01 |
	ENUM_DMA_CFG_STOP);


	/* Number of bytes to be transmitted */
	*pREG_DMA20_XCNT = Message_length

	/* Address increments in bytes */
	*pREG_DMA20_XMOD = M_ONE;

	/*~ GPSB-SDD-FNC-7576 ~*/
	/* Enable the DMA 20 */
	*pREG_DMA20_CFG |= ENUM_DMA_CFG_EN;

	/*
	 * Set the UART0 Interrupt mask to enable Receiver full interrupt and
	 * transmit full interrupt
	 */
	*pREG_UART0_IMSK_SET = M_THREE;


}

Extending no. of HADC inputs with external MUX

GGG — Mon, 07 Oct 2024 15:35:48 GMT

Hi,

I see this is possible for some of the other parts within the family via dedicated MUX pins on PortF, but these are not available on the SC584.

Is there any reason why this could not be done using an external MUX and GPIO pins on this processor?

Thanks,

Various questions/problems regarding SSL and adi_rom_Boot() API

3lions — Mon, 30 Sep 2024 06:27:55 GMT

Hi there,

I'm attempting to implement a second stage loader and am using the SC573_SSL.zip project provided here:ADSP-SC572 Second stage loader won't boot main app with ad-_rom_boot() as a starting point. However, I've found that it is unable to boot my "custom" application, and that even with the Blink application code it's a bit fragile.

I've verified that my application loads and executes correctly when programmed into offset 0x0000 on the SPI2 Flash, however it does not execute when launched by the SSL. I'm having a hard time debugging this, and would appreciate some guidance. In addition, the following things are puzzling me.

In the example Blink application, why is the adi_mmu_init() function defined/overridden? I can see why the cache should not be initialized by the SSL, but why prevent it being used by the final application? Is it necessary to disable the cache in the the application?
The example SSL project includes a linker script "adsp-sc573_L2.ld" but I don't see how the build tools are using that file. See also "apt-sc573.c".
In the comments within the post I've linked to above, I noticed that the boot stream for the SSL includes the "-initcode" flag, but the Blink application doesn't. Are we prevented from including the initcode in both the SSL and application boot streams?
I'd like to use UART0 to output debug data from the SSL However, if I run either of these functions in the SSL, the Blink application no-longer boots:

adi_pwr_Init(CGU_DEV, CLKIN)
Init_UART() // copied from the POST test

Thanks in advance!