# Why do I need to configure CDU: Use case example?

Following scenario describes how CDU along with two CGUs can help in achieving given clocking requirements:

Consider the end application has following clocking requirements:

Core0 = 225 MHz

Core1/Core2 = 450 MHz

DDR clock = 450 MHz

SYSCLK = 225 MHz

S0CLK = 112.5 MHz

S1CLK = 112.5 MHz

GigE = 125 MHz

SDIO/MSI = 50 MHz

In order to achieve these clocking requirement a CLKIN0 = 25 MHz is needed. Even though CGU1 can be run on a seperate CLKIN(CLKIN1) but for this case it is not needed.

CGU0 can be configured with following settings: MSEL=18, DF=0, CSEL=1, SYSSEL=2, S0SEL=2, S1SEL=2, DSEL=1 OSEL=5

This results in following Clocks from CGU0: CCLK = 450 MHz, SYSCLK 225 MHz, S0CLk = 112.5 MHz, S1CLK = 112.5 MHz, DCLK = 450 MHz, OCLK =90 MHz

CGU1 can be configured with following settings: MSEL=20, DF=0, CSEL=10, SYSSEL=2, S0SEL=2, S1SEL=2, DSEL=2 OSEL=5

This results in following Clocks from CGU1: CCLK = 50 MHz, SYSCLK 250 MHz, S0CLK = 125 MHz, S1CLK = 125 MHz, DCLK = 250 MHz, OCLK =100 MHz

With these clocks avaliable from CGU0 and CGU1, CDU can be configured to get the desired clock configuration as follows:

CDU_CFG0.SEL = 0        // Selects CCLK from CGU0 for SHARC core1 which is 450 MHz

CDU_CFG1.SEL = 0        // Selects CCLK from CGU0 for SHARC core2 which is 450 MHz

CDU_CFG2.SEL = 1        // Selects SYSCLK from CGU0 for ARM core0 whichis 225MHz

CDU_CFG3.SEL = 0        // Selects DCLK from CGU0 for DDR clock which is 450 MHz

CDU_CFG7.SEL = 1        // Selects SCLK1 from CGU1 for GigE clock which is 125 MHz

CDU_CFG9.SEL = 2        // Selects CCLK from CGU1 for SDIO/MSI clock which is 50 MHz

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