I have written SPDIF_TalkThrough code on evaluation board ADSP-SC584 where SPDIF Reciever get audio at 96 KHz sample rate and through SPORT 0B get audio in memory and process it and then send processed audio through SPORT 0A to SPDIF Transmitter.
SPDIF Receiver provides Bit Clock, FS and HFCLK to SPORTS as well as to SPDIF Transmitter. I connect SPDIF0_RX_TDMCLK_O to SPDIF0_TX_HFCLK_I to provide HFCLK for Transmitter. But SPDIF0_RX_TDMCLK_O is not accurate at it misses pluses. On Page 37-4 of processor Hardware manual it is written,
The module clock of the S/PDIF transceiver is SCLK0_0. The clock source for the S/PDIF receiver reference clockis CLKO5 from the CDU. When CLKO5 is configured, it supports sampling frequencies of 24 kHz to 192 kHz.The clock to this module may be shut off for power savings.Sample rates of 24 kHz to 96 kHz are supported using a 170 MHz to 180 MHz setting on CLKO5.Sample rates of 32 kHz to 192 kHz are supported using a 225.0 MHz setting on CLKO5.
even at setting of 225 MHz, it is highly in accurate.
Can u provide the solution how can I use SPDIF0_RX_TDMCLK_O clock for SPDIF0_TX_HFCLK_I at 96 KHZ?
Did you ever resolve this? I understand exactly what you're asking and I want to do the same. I also want to align the transmitted SPDIF preambles to the received preambles (in accordance with AES3 standard) but I cannot find any documentation of the SPDIF_TX_EXTSYNC signal (whose name and position on the block diagram seem promising, but connecting it doesn't seem to do much).Regards,CH
Hello,I don’t think there is anything in AES 3 which restricts users to have transmit and receive preamble to be in sync. SPDIF TX and RX are independent. Can you please let me know Is this the reqirement in your application? Please elaborate with more details on your system.The anomaly 20000094 (PageNo:34/34) directs users to not use SPDIF_TDM_MCLK_O as it a known problem. Please find the anomaly sheet from below link,www.analog.com/.../ADSP-2158x_ADSP-SC58x-SHARC-Anomaly.pdfPlease note that the SPDIF_TX_EXTSYNC is a rising edge on this pin, it resets SPDIF TX internal counters and SPDIF signal starts sending from First subframe of its 192 Sub frames.Regards,Anand Selvaraj.