I have written SPDIF_TalkThrough code on evaluation board ADSP-SC584 where SPDIF Reciever get audio at 96 KHz sample rate and through SPORT 0B get audio in memory and process it and then send processed audio through SPORT 0A to SPDIF Transmitter.
SPDIF Receiver provides Bit Clock, FS and HFCLK to SPORTS as well as to SPDIF Transmitter. I connect SPDIF0_RX_TDMCLK_O to SPDIF0_TX_HFCLK_I to provide HFCLK for Transmitter. But SPDIF0_RX_TDMCLK_O is not accurate at it misses pluses. On Page 37-4 of processor Hardware manual it is written,
The module clock of the S/PDIF transceiver is SCLK0_0. The clock source for the S/PDIF receiver reference clockis CLKO5 from the CDU. When CLKO5 is configured, it supports sampling frequencies of 24 kHz to 192 kHz.The clock to this module may be shut off for power savings.Sample rates of 24 kHz to 96 kHz are supported using a 170 MHz to 180 MHz setting on CLKO5.Sample rates of 32 kHz to 192 kHz are supported using a 225.0 MHz setting on CLKO5.
even at setting of 225 MHz, it is highly in accurate.
Can u provide the solution how can I use SPDIF0_RX_TDMCLK_O clock for SPDIF0_TX_HFCLK_I at 96 KHZ?
Sorry for the delay in getting back on this. You would use Precision Clock Generators (PCG ) to provide clock signal to SPDIF. Th PCG produces a pair of signals from a clock input signal. The two signals generated are normally used as a serial bit clock and frame sync pair.
You would refer the code example provide in the following Ezone thread, ADSP-SC58x/2158x SPDIF: Example code
For more information on PCG, please refer to ADSP-SC58x Hardware reference manual
can you confirm that there is a hardware bug to use SPDIF0_RX_TDMCLK_O clock for SPDIF0_TX_HFCLK_I at 96 KHZ?
I do not want to use PCG because in that case i have to use ASRC to achieve synchronization with outside signal. That will cause latency and increase noise floor.
Not sure if its still open, apologies in case you could not resolve this in quickly. When using PCG, why you want to use ASRC to achieve synchronization with outside signal?
Can you try using PCG only to generate HFCLK not bitclock and FS, if you use this approach, there is no need for the ASRC in the frame work. BCLK and FS you can use from SPDIF-RX it self.