PCG C & D not working

Hi,

So far I have been using only PCG A & B in my project (for DAI0). Now I have a new use case where I want to use DAI1 which in turn require setting up of PCG C & D. I tried to initialize PCG C in a similar way as I was initializing PCG A & B. But I am not getting any clock outputs (CLK  FS)  from PCGC. Attaching the pcg-init code. Please take a look at it and help me to figure out what's going wrong!

Thanks & Regards,

Aswin

attachments.zip
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  • Hello,

    I seem to have the same problem. PCGC and PCGD are not working, but A and B are. What do you mean by 'devicenum'?
    As far as I know there is only one PCG, PCG0...

    My code;

    	SRU2(HIGH, 	DAI1_PBEN10_I);       // Set debug dai pin to output
    	SRU2(HIGH, 	DAI1_PBEN09_I);       // Set debug dai pin to output
    
    	// route ADAU1761 BCLK signal to PCGD external clock input
    	SRU2(DAI1_CRS_PB03_O, PCG0_EXTCLKD_I);
    
    	// route ADAU1761 FS signal to sync input
    	SRU2(DAI1_CRS_PB04_O, PCG0_SYNC_CLKD_I);
    
    	// Set up the Precision Clock Generator (PCG) to divide our bit clock by 4 or 8
    	*pREG_PCG0_SYNC2 =	BITM_PCG_SYNC2_FSD   |    // Enable external FS synchronization
    						BITM_PCG_SYNC2_CLKD   |     // Enable external FS synchronization
    						0;
    
    	*pREG_PCG0_CTLD1 =	BITM_PCG_CTLD1_CLKSRC |  // Set BCLK source as PCG_EXT_I
    					   	BITM_PCG_CTLD1_FSSRC  |   // Set FS source as PCG_EXT_I
    						4 |
    						0;
    
    	*pREG_PCG0_CTLD0 =	BITM_PCG_CTLD0_CLKEN |     // Enable CLK output
    						BITM_PCG_CTLD0_FSEN     |   // Enable FS output
    						256   |     // FS Div = 256fs or 512fs
    						0;
    
    	SRU2(PCG0_CLKD_O, DAI1_PB10_I);
    	SRU2(PCG0_FSD_O, DAI1_PB09_I);