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PCG C & D not working


So far I have been using only PCG A & B in my project (for DAI0). Now I have a new use case where I want to use DAI1 which in turn require setting up of PCG C & D. I tried to initialize PCG C in a similar way as I was initializing PCG A & B. But I am not getting any clock outputs (CLK  FS)  from PCGC. Attaching the pcg-init code. Please take a look at it and help me to figure out what's going wrong!

Thanks & Regards,

  • Hi Aswin,

    Please let me know which processor are you reffing to?

    Your attached code doesn't have any SRu routing information, can you please share the same?



  • Hi Jithul,

    Thanks for your response.

    I am using sc589. Please find attached sru-config file along with the pcg-settings file and also the clocking design diagram.
    - ADAU1761 Codec is connected to sc589.
    - Configured Codec such that DSP receives LRCK (On DAI0_PB04) & BCLK (On DAI0_PB03) from the Codec.

    - PCGA uses DAI0_03_O EXTERNAL_CLK (12.288MHz) to generate CLKA (3.072MHz) & FSA (48KHz)

    - Probed and verified DAI0_PB03_O & DAI0_PB04_O

    - Probed and verified CLKA & FSA

    - PCGC uses DAI1_CRS_03_O EXTERNAL_CLK 12.288MHz to generate CLKC (3.072MHz) & FSC (48KHz)

    - When probed CLKC & FSC they are not present.

    - When probed DAI1_CRS_03_O & DAI1_CRS_04_O, they are also not present.

    How do I take the clock present in DAI0_PIN03 & DAI0_PIN04 to PCGC ? My understanding was that it's via Share pin buffer.  But due to some reason, this is not working.



  • Hi Jithul,

    Figured it out. I was using wrong DeviceNum for PCGC & D. Instead of using 2 for PCGC & 3 for PCGD, I was using 0 for both (copy-paste mistake).

    Anyway, thanks for offering your support.


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  • Hello,

    I seem to have the same problem. PCGC and PCGD are not working, but A and B are. What do you mean by 'devicenum'?
    As far as I know there is only one PCG, PCG0...

    My code;

    	SRU2(HIGH, 	DAI1_PBEN10_I);       // Set debug dai pin to output
    	SRU2(HIGH, 	DAI1_PBEN09_I);       // Set debug dai pin to output
    	// route ADAU1761 BCLK signal to PCGD external clock input
    	// route ADAU1761 FS signal to sync input
    	// Set up the Precision Clock Generator (PCG) to divide our bit clock by 4 or 8
    	*pREG_PCG0_SYNC2 =	BITM_PCG_SYNC2_FSD   |    // Enable external FS synchronization
    						BITM_PCG_SYNC2_CLKD   |     // Enable external FS synchronization
    	*pREG_PCG0_CTLD1 =	BITM_PCG_CTLD1_CLKSRC |  // Set BCLK source as PCG_EXT_I
    					   	BITM_PCG_CTLD1_FSSRC  |   // Set FS source as PCG_EXT_I
    						4 |
    	*pREG_PCG0_CTLD0 =	BITM_PCG_CTLD0_CLKEN |     // Enable CLK output
    						BITM_PCG_CTLD0_FSEN     |   // Enable FS output
    						256   |     // FS Div = 256fs or 512fs
    	SRU2(PCG0_CLKD_O, DAI1_PB10_I);
    	SRU2(PCG0_FSD_O, DAI1_PB09_I);

  • Hi,

    Could you please download the PCG code from FAQ : "ADSP-SC58x/2158x PCG : Example codes" in below link.

    Anand Selvaraj.