Memory gaps inserted between different sections in L1 block

Linker memory gaps:


I'm working on a static library (.DLB) and a CCES project that uses the DLB and building a .DXE file to run on ADSP21584. When building the DXE file I'm noticing memory gaps that seem to be created by the linker. The LDF includes memory allocation of sections from both the main project and


the dlb. In my LDF i define the memory block addresses as follows:


mem_block2_a_bw  { TYPE(BW RAM) START(0x00300000) END(0x00300003)    WIDTH(8) }

mem_block2_b_bw  { TYPE(BW RAM) START(0x00300004) END(0x00318FFF)    WIDTH(8) }



The mapping of the output sections is (In_Sec_b is used in the DLB project):


dxe_block2_a BW




           } > mem_block2_a_bw  


     dxe_block2_b BW




           } > mem_block2_b_bw 




In_sec_a includes:


#pragma section("In_Sec_a")

float32 *pa;


In_Sec_b includes:


#pragma section("In_Sec_b")

static Float32_t arr[24137];



After the build, the memory map shows that "pa" is allocated to address 0x00300000, but "arr[]" is allocated to address 0x00300008, instead of 0x00300004  and there is also where the output section dxe_block2_b starts. .  There seem to be 4 bytes between the 2 sections. This seems wrong since the alignment is correct. See memory map screenshot for details.

Can anyone help here?

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