Memory gaps inserted between different sections in L1 block

Linker memory gaps:

 

I'm working on a static library (.DLB) and a CCES project that uses the DLB and building a .DXE file to run on ADSP21584. When building the DXE file I'm noticing memory gaps that seem to be created by the linker. The LDF includes memory allocation of sections from both the main project and

 

the dlb. In my LDF i define the memory block addresses as follows:

 

mem_block2_a_bw  { TYPE(BW RAM) START(0x00300000) END(0x00300003)    WIDTH(8) }

mem_block2_b_bw  { TYPE(BW RAM) START(0x00300004) END(0x00318FFF)    WIDTH(8) }

 

 

The mapping of the output sections is (In_Sec_b is used in the DLB project):

 

dxe_block2_a BW

{

                INPUT_SECTION_ALIGN(4)

                INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(In_Sec_a) )

           } > mem_block2_a_bw  

 

     dxe_block2_b BW

           {

                INPUT_SECTION_ALIGN(4)

                INPUT_SECTIONS( $OBJS_LIBS_NOT_EXTERNAL(In_Sec_b) )

           } > mem_block2_b_bw 

 

 

 

In_sec_a includes:

 

#pragma section("In_Sec_a")

float32 *pa;

 

In_Sec_b includes:

 

#pragma section("In_Sec_b")

static Float32_t arr[24137];

 

 

After the build, the memory map shows that "pa" is allocated to address 0x00300000, but "arr[]" is allocated to address 0x00300008, instead of 0x00300004  and there is also where the output section dxe_block2_b starts. .  There seem to be 4 bytes between the 2 sections. This seems wrong since the alignment is correct. See memory map screenshot for details.

Can anyone help here?

Thanks!

attachments.zip
  • 0
    •  Analog Employees 
    on Feb 22, 2018 11:02 AM

    Hi,

    We understand that you have already contacted our private support.Please continue the discussion there.We are posting the response here for others to benefit.

    Global arrays must be aligned on a 64-bit word boundary or greater; the compiler will normally use this knowledge when optimizing accesses.

    Hence data object "arr" is placed on a address that is evenly divisible by eight.

    Please refer in the CCES help:
    CrossCoreRegistered Embedded Studio 2.7.0 > SHARCRegistered Development Tools Documentation > C/C++ Compiler Manual for SHARCRegistered Processors > Compiler > C/C++ Run-Time Model and Environment > Global Array Alignment

    For better understanding we provide the below example:

    We have used the Memory and object section that you shared:

    In source code:
    #pragma section("In_Sec_a")
    char element1;  /* alignment 1 and 1 byte of padding */

    #pragma section("In_Sec_a")
    short element2; /* alignment 2 and no padding*/

    #pragma section("In_Sec_b")
    static float32_t element3[24137];  /* alignment 8 - stored in the location of 0x300008, since Global arrays address should be divisible by 8 */

    By default, the compiler inserts any necessary padding to ensure that elements are aligned on their required boundaries.

    Regards,

    Kader

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:02 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin