Post Go back to editing

Getting processed DMA buffer in SPORT group callback

Thread Summary

The user is experiencing issues with the SPORT DMA group configuration on the ADSP-SC59x processor, where the SPORT_DMA_DSCPTR_PRV register sometimes points to the wrong buffer during the first interrupt. The final answer suggests checking the 'Register Polling Based Synchronization' section in the Hardware Reference Manual for detailed information on DMA synchronization. The user seeks further clarification on why the DMA registers do not reflect the current operation status and asks for documentation on this behavior.
AI Generated Content
Category: Software

Hi Team,

This about how to get the processed SPORT DMA data buffer in group configuration.

The API adi_sport_GlobalRegisterCallback(), takes the callback function of type void (*ADI_CALLBACK)(void *pCBParam, uint32_t Event, void *pArg), where pArg points to the group handle.

In case of single SPORT config the call back function registered adi_sport_RegisterCallback() returns the processed buffer in pArg which is convinient. I understand it is not possible to pass the processed buffer in the group case as mutiple SPORTs are involved.

In our case, we have configured the multiple SPORT DMA with two DMA descriptors

ping ---> 0th index

pong ----> 1st index

in a circular configuration and grouped them together.

In the group callback, currently we are getting the completed buffer address from the SPORT_DMA_DSCPTR_PRV register of the specific SPORT, with the understanding that it points to the previous descriptor which is already processed by DMA

But the issue is sometimes during the very first interrupt, SPORT_DMA_DSCPTR_PRV points to pong buffer instead of ping.

1. Could you please explain the reason for such behaviour? 

2. What is the recommeded way to get the processed buffer in the group callback case? Should we use a ping / pong flag to determine the buffer?

3. The internal struct in SPORT driver ADI_SPORT_GBL_GROUP has a member 'nBufferIndex' which could be helpful to determine the buffer. Is this exposed to user in any of the interface?

typedef volatile struct
{
  ADI_SPORT_HANDLE         *pDeviceArray;
  uint8_t             NoofDevices;
  bool                      bUsed;
  bool            bGblTrigEnable;
    ADI_CALLBACK              pfCallback;
    void                     *pCBParam;
    bool            bGroupInProgress;
    uint8_t           nBufferIndex;
    bool            bCircularBuff;
} ADI_SPORT_GBL_GROUP;

Thanks in advace.

Regards,

Vetrivel.

  • Hi Vetrivel,

    Regarding Q1 and Q2, the DMA current address, pointer, and count registers may update several cycles in advance of the completion of the corresponding memory operation. Therefore, this timing is measurable from the time at which the results of the operation are first visible to the core by memory read or write instructions and they may not accurately indicate the exact completion of a DMA transfer.

    So, please do not poll the DMA channel registers (DMA_ADDR_CUR, DMA_DSCPTR_CUR, DMA_XCNT_CUR, or DMA_YCNT_CUR) as a method of precisely synchronizing DMA with data processing, as it's not recommended.

    Instead for synchronization, we suggest using “CallbackCount” variable implemented in the Audio_Loopback_TDM example.

    Regarding Q3, the ADI_SPORT_GBL_GROUP structure is intended only for internal use by the SPORT driver and it should not be accessed directly in your application.

    Regards,
    Nandini C

  • Hi Nandini,

    Thank you for the feedback. We will implement the callback as recommended.

    But from the explanation it is still not clear for us, why the DMA registers does not refelect the current DMA operation status. For example,with our SPORT configuration DMA interrupt will be triggered once in every 83us. If the registers are updated serveral cycle in adavance before the completion of the memory operation and then the interrupt is triggered our expectation is that there will no change in the registers atleast for the half of the 83us period.

    Could you please point to any documentation which explains the scenario you metioned in detial? 

    Also any documentation which sugest not to use these registers for sync will be helpful.

    Regards,

    Vetrivel.

  • Dear Vetrivel,

    We assume that you are using ADSP-SC59x processor for your application.

    If so, you can find detailed information in the “Register Polling Based Synchronization” section under the DMA chapter of the Hardware reference manual regarding the synchronization in the link below.
    https://www.analog.com/media/en/dsp-documentation/processor-manuals/adsp-2159x-sc591-592-594-hrm.pdf

    Hope this helps.

    Regards,
    Nandini C

  • Hi Nandini,

    Thanks for the pointers to the document.

    We can close this thread.

    Regards,

    Vetrivel.