GPI interrupt on both edges, PINT and related.

Hello, I'm really, really confused about how GPIO pins, PINT and SEC are intended to be used in combination to generate user-defined interrupts for different events (level, edges), ports and pins.

The first headache came when I tried to understand the mapping of the ports/pins on the PINTs:

As far as I can understand from the above diagram:

• PINT0 can generate interrupts for pins on PORT A and B, PINT1 can generate interrupts for pins on PORT B and C, while PINT2 can only generate interrupts for pins on PORT C.
• Individually for each pin configured in each PINT, we can decide to which port the pin belongs to (e.g. for PINT0 we can configure if a pin belongs to port A or port B) and to which event we would like to be sensitive to (i.e. high level, low level, rising edge or falling edge).

The second headache came later when trying to enable an interrupt on both rising and falling edges on the same pin using the same PINT, which I solved in a completely fortuitous way by searching for help on Google and finding this link:

Single interrupt block for both rising and falling edges in ADSP-21569 - Documents - CrossCore Embedded Studio and Add-ins - EngineerZone

in which PC07 and PC23 (????) are successfully used to setup rising-edge and falling-edge interrupts, respectively, using PINT1 on the same physical pin PC07, calling adi_gpio_RegisterCallback() two times for setting up the same callback on both events.... and the following points remained to be clarified:

• each PINT (0, 1, 2) can generate one IRQ (and only one) for each pin mapped, so even if ADI_GPIO_RESULT adi_gpio_RegisterCallback(ADI_GPIO_PIN_INTERRUPT const ePinInt,
  uint32_t const Pins, ADI_GPIO_CALLBACK const pfCallback, void * const pCBParam) function gives the impression that we can install a different callback on different pins belonging to the same PINT, this is just a "software illusion" and we never need to install more than 3 callbacks (one per each PINT block) to handle all the interrupts in this world.... am I right?
• since physical GPIO pins on all ports are numbered from 0 to 15, what are the pins numbered from 16 to 31 appearing in adi_gpio.h (see screenshot below)? Looks like they're the equivalent of pins 0-15 but left-shifted by 16 bits for the sole purpose of addressing upper BYTE2 and BYTE3 part of registers like REG_PINT0_INV_CLR when passing "pins" parameter to functions like adi_gpio_PinInt()? If so, why does everything have to be so complicated and counterintuitive?