How to transfer clock and data from DAI0 to DAI1?

Hi Yunhe,

Regarding " Is this data transmission mode reasonable?
>> Yes, using SPORT0 to receive data from DAI0 and SPORT4 to transmit data to DAI1 is a reasonable data transmission mode. Please ensure that both SPORT0 and SPORT4 are clocked from the same bit clock (BCLK) and frame sync (FS). SPORT4 should output the same clock and FS signals to DAI1.

Regarding "Transferring sport0 to sport4: Transferring through adi_Sport_SMATransfer???"
>> Yes, you can use the adi_sport_DMATransfer() API to transfer data.

Regarding "Only pins PB03~PB06 correspond to each other?"
>> The CRS method only supports specific pins (PB03–PB06). However, you can connect as follows if you are not already using DAI pins 3 and 4:
SRU(DAI0_PB01_O, DAI0_PB03_I);
SRU2(DAI1_CRS_PB03_O,SPT4_ACLK_I );

Similarly, for frame sync:
SRU(DAI0_PB02_O, DAI0_PB04_I);
SRU2(DAI1_CRS_PB04_O, SPT4_AFS_I );

This allows peripherals on both DAI0 (e.g., SPORT 0A) and DAI1 (e.g., SPORT 4A) to share the same Clock and Frame Sync signal, maintaining synchronization.

Regards,
Nandini C

Hi NandiniC

Thank you for your reply.
The CRS method only supports specific pins (PB03–PB06). However, you can connect as follows if you are not already using DAI pins 3 and 4:
SRU(DAI0_PB01_O, DAI0_PB03_I);

==>I understand what you mean, but our current hardware connection already uses PB03, PB04, PB05, and PB06 as data interfaces. How should we operate them? Is there any other plan to implement it?

Hi NandiniC
There is another question, can DAI1 use an external clock like DAI0, supplied by TDM, so that ADSP no longer transfers the clock from DAI0 to DAI1 internally? Can data be transferred from sport0 to sport1?
Thanks

Hi Yunhe,

Based on the hardware constraints where pins PB03–PB06 are already used for data interfaces, please refer the following approach for clock and data transfer between DAI0 and DAI1:

DAI1 will receive its clock and frame sync signals directly from the external TDM source, just like DAI0. This eliminates the need for internal routing of clock and frame sync signals between DAI0 and DAI1, thereby bypassing the CRS method entirely. This ensures both DAIs are properly synchronized to the same external timing source.

For transferring the data stream from DAI0 to DAI1, we can use the DMA controller as you mentioned earlier. Use SPORT0's DMA channel to move data from SPORT0’s receive buffer into a memory. Use SPORT4's DMA channel to move data from the memory buffer into SPORT4’s transmit buffer. SPORT4 will then output the data through DAI1 to the A2B chip.

This approach avoids pin conflicts, maintains synchronization through an external clock, and uses DMA for efficient data transfer.

Regards,
Nandini C

Hi NandiniC,

We are currently using the following method to achieve clock frequency transfer from DAI0 to DAI1. Could you please help us check if this method is feasible?
Transferred through PCG.

I am not sure if it is necessary to configure pREG_PCG0_CTLA1/pREG_PCG0_CTLA0/pREG_PCG0_CTLB0/pREG_PCG0_CTLB1.

The clock frequency received by DAI0 is 48kHz/32bit/16slot,
How to set pREG_PCG0_CTLA1???

#if 1   //i2s6 to DAI0
    //////////////     CLK Routing      //////////////
        SRU(DAI0_PB01_O, PCG0_EXTCLKA_I);// DAI1_PB09 CLK input as PCG0 INPUT CLK
        SRU(DAI0_PB01_O,SPT0_BCLK_I); /*DAC clock to SPORT 0B*/
        SRU(LOW, DAI0_PBEN01_I);

    	SRU(DAI0_PB02_O, PCG0_EXTCLKB_I);// DAI1_PB10 SYNC input as PCG0 INPUT SYNC
    	SRU(DAI0_PB02_O,SPT0_BFS_I);  /*DAC FS to SPORT 0B*/
    	SRU(LOW, DAI0_PBEN02_I);


    	SRU2(PCG0_CRS_CLKA_O, DAI1_PB01_I);//CLK Output
    	SRU2(HIGH, DAI1_PBEN01_I);

    	SRU2(PCG0_CRS_CLKB_O, DAI1_PB02_I);//FS Output
    	SRU2(HIGH, DAI1_PBEN02_I);

        SRU2(DAI1_PB01_O,SPT4_ACLK_I); /*DAC clock to SPORT 0A*/
        SRU2(DAI1_PB02_O,SPT4_AFS_I);  /*DAC FS to SPORT 0A*/

        SRU2(SPT4_AD0_O,DAI1_PB05_I); /* SPORT 4A to DAC*/
        SRU2(HIGH,DAI1_PBEN05_I);//21569 output data to DAC

        SRU2(SPT4_AD1_O,DAI1_PB06_I); /* SPORT 4A to DAC*/
        SRU(HIGH,DAI1_PBEN06_I);//21569 output data to DAC


        SRU(DAI0_PB05_O,SPT0_BD0_I);/* ADC to SPORT 0B*/
        SRU(LOW,DAI0_PBEN05_I);//ADC data input to 21569

        SRU(DAI0_PB06_O,SPT0_BD1_I);/* ADC to SPORT0B*/
        SRU(LOW,DAI0_PBEN06_I);//ADC data input to 21569

#endif

        int clock_divider_CLK =1U;  // Input CLK=3.072M
    	int clock_divider_FS = 1U;  // Input FS=48K

    	*pREG_PCG0_CTLA1 = BITM_PCG_CTLA1_CLKSRC |     // Set BCLK source from externl
    						BITM_PCG_CTLA1_FSSRC  |
    						clock_divider_CLK |
    						0;


    	*pREG_PCG0_CTLA0 = BITM_PCG_CTLA0_CLKEN |      // Enable CLK output
    						BITM_PCG_CTLA0_FSEN |
    						clock_divider_FS  |
    						0;

    	*pREG_PCG0_CTLB1 = BITM_PCG_CTLB1_CLKSRC |
    							BITM_PCG_CTLB1_FSSRC | // Set FS source as from_externl
    							clock_divider_CLK |
    							0;


    	*pREG_PCG0_CTLB0 = BITM_PCG_CTLB0_CLKEN |
    							BITM_PCG_CTLB0_FSEN |   // Enable FS output
    							clock_divider_FS  |
    							0;

}

Hi Yunhe,

Yes, the method you are using to interconnect DAI1 and DAI0 seems correct. As per the ADSP-2156x HRM, when CLKDIV and FSDIV are set to 0 or 1, the PCG operates in bypass mode, meaning that the input clock is passed directly to the output. Also, "Table 22-7: DAI1 Routing Capabilities"(Page No: 989/2453) confirms that the PCG cross pins can be routed to DAI0.

We have a reference example code in our BSP that is similar to your requirement. The BSP can be downloaded from the link below:download.analog.com/.../ADI_EV-2156x_EZ-KIT-Rel3.0.0.exe

After installation, please navigate to the following path:
<installation path>\Analog Devices\EV-2156x_EZ-KIT-Rel3.0.0\EV-2156x_EZ-KIT\Examples\drivers\adc\SPDIF_ASRC_DAC_AudioPassthrough

Regards,
Nandini C