Clock Generation Unit (CGU)

Hi,

The "Core Clock Buffer Disable Register" manages the clock buffer for each core, determining whether the CCLK is enabled. The "System Clock Buffer Disable Register" controls the clock buffer for each system, determining whether the SCLKn buffer is enabled. These bits are enabled by default.

For detailed information on controlling the clock buffer, please refer to the CGU_CCBF_DIS register fields(Pg:No: 166) and CGU_SCBF_DIS register fields (Pg:No: 180) in the ADSP-SC58x HRM linked below.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/SC58x-2158x-hrm.pdf

To get the "C" based example code, you can download and install the BSP for ADSP-SC5XX from the following link:
download.analog.com/.../ADI_ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2.exe

After successful installation, the example code can be found at the following path:
<installation path>\Analog Devices\ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2\ADSP-SC5xx_EZ-KIT\Examples\services\power

For detailed instructions on the example, please refer to the "readme" file included within the example folder.
Also, you can refer the init code from the CCES installation path:
<installation path>\Analog Devices\CrossCore Embedded Studio 2.x.x\SHARC\ldr\init_code\SC58x_Init

While we don't have example code based on assembly for the ADSP-SC58x processor, you can refer to the C code as a reference to develop your application.

You can also refer to the following Ezone thread, which contains a use case example for configuring the CDU. This might be helpful for your reference.
https://ez.analog.com/dsp/sharc-processors/adsp-sc5xxadsp-215xx/f/q-a/64186/why-do-i-need-to-configure-cdu-use-case-example

Regards,
Nandini.C