Hello,
I am simulating my layout of the DDR3 interface using the IBIS model of the ADSP-SC584 which I downloaded from the analog devices website. I am using the same DDR3 chip as the one used on the ADZS-SC589-EZLITE board.
When running the simulation, it fails the signal integrety test for the address lines due to the setup time being to short because the edges of the address are very slow. The drive strength of the address lines (which are fixed to 60 Ohms in the IBIS model) seems to be to slow. However on the ADZS-SC589-EZLITE board the init code also configures the drive impedance to 60 Ohms. And as my address lines are shorter than the ones in that design I expect a simulation it would also fail for that board. However, clearly it works in the real world as it is a dev board and i have it working here on my desk.
Is the IBIS model of the DSP outdated or not correct?
