Post Go back to editing

Driver for SPI0 Register based

Category: Software
Product Number: ADSP-SC571

I am currently trying to put the SPI0 interface into operation and create a register-based driver. This is to be able to communicate with the basic device.

The basic device sends commands that are either 1 or 3 bytes long. I have currently initialised the interface and then read out the fifo. Basically, however, I receive this data in a non-reproducible sequence and with shifts. What am I doing wrong?


*pREG_SPI0_CTL = (BITM_SPI_CTL_EN | !BITM_SPI_CTL_MSTR | BITM_SPI_CTL_ASSEL); //Config SPI0 as a slave, active high SPI CLK, 8 bit word, MSB

I was able to determine the correct data on the lines with a logic analyser (see picture)

Can anyone help me?

  • Hi,

    Please refer to the ADSP-SC58x/2158x FAQ link below for data transfer using SPI peripheral. It can be used for core mode or DMA mode data transfer. Please take this as reference code and modify it as per your requirement for ADSP-SC571 and try communicating with your device.

    Please also refer to the sections "SPI Programming Concepts" (page:627) and "Control Register" (page:634) in the HRM link below:

    Ranjitha R

  • Hi Ranjitha,

    Thanks for the answer and the sample code.

    Do I understand correctly that an interrupt e.g. "Receive Finish Indication" is only dependent on the SPI_RWC? This is of course very helpful if data of the same length is always expected, but if this is not the case, as is the case with me now (1 or 3 bytes), I cannot detect the end 

    Is there no status that refers to the SS_Input, because then I would know after a received byte whether it is finished or whether there are two more to come.

    Or is there another way to read this data in slave mode without DMA?

    Thank you for your help!



  • Hi Dominik,

    Yes, you are correct, that the interrupt "Receive Finish Indication" is dependent on the SPI_RWC.

    Is our understanding of your requirement right, you want to know if an interrupt or status bit is available after receiving the data from the Master of any length irrespective of the defined word count size of the receiving buffer?

    As per the SPI communication, once the transmit interrupt occurs, the data will start transmitting and the buffer will expect the defined length to ensure all the data has been received and generate an interrupt which will the assert the SS pin to be high indicating to stop data reception.

    When you send a data length shorter than the defined size, the remaining size is appended with zeros to the transmitting frame.
    So, it is recommended to add zeros while transmitting for the remaining size to ensure only expected data is transmitted.

    Ranjitha R