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Need to reset SPU before calling adi_rom_boot() in application of ADSP-21593

Category: Software
Product Number: ADSP-21593
Software Version: CCES 2.11.1.0

Hello,

In SSL(second-stage-loader) application, I use UART DMA to receive data, so the SPU is configured,

after that, when calling adi_rom_boot() function, it will fall.

but if I add a function to reset SPU before calling adi_rom_boot() function, it will success.

so, my question is: is there some documents or examples to tell me how do deal with this situation?

 

the following are the spu reset codes:

void hw_spu_deInit(void)
{
	/*Unlock*/
	adi_spu_EnableGlobalLock(hSpu, false);
	adi_spu_LockWriteProtectionConfig(hSpu, false);

	/*Disable SPU functions*/
	adi_spu_EnablePotectionViolationInt(hSpu, false);
	adi_spu_EnableSecurityViolationInt(hSpu, false);
	adi_spu_LockSecureConfig(hSpu, false);

	adi_spu_ClearSlaveSecure(hSpu);
	adi_spu_ClearMasterSecure(hSpu);
	adi_spu_EnableCoreAndL1MemSecure(hSpu, ADI_CORE_SHARC0, false);

	/***************************************************************************/
	/*Uninit UART0*/
	adi_spu_EnableMasterSecure(hSpu, UART_DEVA_SPU_PID, false);
	adi_spu_EnableMasterSecure(hSpu, UART_DEVA_TxDMA_SPU_PID, false);
	adi_spu_EnableMasterSecure(hSpu, UART_DEVA_RxDMA_SPU_PID, false);

	/***************************************************************************/
	/*Uninit LINKPORT*/
	adi_spu_EnableMasterSlaveSecure(3,false,false);
	adi_spu_EnableMasterSlaveSecure(4,false,false);
	adi_spu_EnableMasterSlaveSecure(5,false,false);
	adi_spu_EnableMasterSlaveSecure(6,false,false);

	/***************************************************************************/
	/*Release SPU*/
	adi_spu_UnInit(hSpu);
}

the following are the adi_rom_boot() related codes:

uint32_t gApplicationPhysicalStartAddress = 0;
uint32_t gBootCmd;

/*********************************************************************************************/
int ROM_BOOT_HOOK_FUNC1(ADI_ROM_BOOT_CONFIG * pBootConfig, ROM_HOOK_CALL_CAUSE cause)
{
	ADI_SPI_TypeDef * pSpiRegs = ( ADI_SPI_TypeDef *)pBootConfig->pPeripheralBase;
	ADI_ROM_BOOT_SPI * pSpiStruct = ( ADI_ROM_BOOT_SPI *)pBootConfig->pModeData;

	switch(cause){
	case ROM_HOOK_CALL_INIT_COMPLETE :
		asm("NOP;");
		break;
	case ROM_HOOK_CALL_CONFIG_COMPLETE :
		asm("NOP;");
		#if 0
		/*Configure the SPi Memory Mapped registers for 4-byte addressing mode*/
		pSpiRegs-> MMRDH = (((0x13 << BITP_SPI_MMRDH_OPCODE ) 	& BITM_SPI_MMRDH_OPCODE	)	|
						   ((4 		<< BITP_SPI_MMRDH_ADRSIZE) 	& BITM_SPI_MMRDH_ADRSIZE)	|
						   ((0 		<< BITP_SPI_MMRDH_ADRPINS) 	& BITM_SPI_MMRDH_ADRPINS) 	|
						   ((0		<< BITP_SPI_MMRDH_DMYSIZE) 	& BITM_SPI_MMRDH_DMYSIZE) 	|
						   ((0x00 	<< BITP_SPI_MMRDH_MODE	)	& BITM_SPI_MMRDH_MODE	)	|
						   ((1 		<< BITP_SPI_MMRDH_TRIDMY)	& BITM_SPI_MMRDH_TRIDMY	)	|
						   ((1 		<< BITP_SPI_MMRDH_MERGE	)	& BITM_SPI_MMRDH_MERGE	)	|
						   ((0  	<< BITP_SPI_MMRDH_WRAP	)	& BITM_SPI_MMRDH_WRAP	)	|
						   ((0 		<< BITP_SPI_MMRDH_CMDSKIP)	& BITM_SPI_MMRDH_CMDSKIP)	|
						   ((0 		<< BITP_SPI_MMRDH_CMDPINS)	& BITM_SPI_MMRDH_CMDPINS)	);

		/* Update the control value uses to support memory mapped mode */
		pBootConfig->dControlValue = BITM_SPI_CTL_EN | BITM_SPI_CTL_MSTR | (0 << BITP_SPI_CTL_SIZE) | ENUM_SPI_CTL_MM_EN | BITM_SPI_CTL_ASSEL;

		/* Enable both transmit and receive parts of the SPI */
		pSpiRegs->TXCTL |= BITM_SPI_TXCTL_TEN | BITM_SPI_TXCTL_TTI;
		pSpiRegs->RXCTL |= BITM_SPI_RXCTL_REN ;

		/* Enable the SPI in memory mapped mode */
		pSpiRegs->CTL = pBootConfig->dControlValue | pSpiStruct->nRxCtl;
		#endif
		break;
	case ROM_HOOK_REG_COMPLETE :
		asm("NOP;");
		break;
	default :
		break;
	}

	return 0;
}

/*Jump to Application*/
/*application_flash_offset: application start address in flash*/
void jump_to_application(uint32_t application_flash_offset)
{
	/*Store application address*/
	/*Must add SPI base address*/
	gApplicationPhysicalStartAddress = 0x60000000 + application_flash_offset;

	/*SPI2 memory mapped boot*/
	/*Boot process reserves 8KB of L2 RAM for use, start at 0x201FE000*/
	*pREG_SHL1C0_CFG2 |= 0xF00;
	*pREG_SHL1C0_RANGE_START4 = 0x201FE000;
	*pREG_SHL1C0_RANGE_END4 = 0x201FFFFF;

	asm("#include <sys/def215xx_core.h>");
	asm("IRPTL = 0;");
	asm("MMASK = BITM_REGF_MMASK_BR8|BITM_REGF_MMASK_BR0|BITM_REGF_MMASK_IRPTEN|BITM_REGF_MMASK_ALUSAT|BITM_REGF_MMASK_TRUNCATE|BITM_REGF_MMASK_PEYEN|BITM_REGF_MMASK_BDCST9|BITM_REGF_MMASK_BDCST1;");
	asm("IMASK = BITM_REGF_IMASK_EMUI|BITM_REGF_IMASK_RSTI|BITM_REGF_IMASK_PARI|BITM_REGF_IMASK_ILOPI|BITM_REGF_IMASK_CB7I|BITM_REGF_IMASK_IICDI|BITM_REGF_IMASK_SOVFI| BITM_REGF_IMASK_ILADI; nop;");
	asm("B7 = 0x201FF400;\
	     I7 = ((0x201FF400 + 0xC00 - 1) - ((0x201FF400 + 0xC00 - 1) % 4) );\
	     L7 = ((0xC00 - ((0x201FF400 + 0xC00 - 1) % 4) ) / 4);\
	     B6 = B7;\
	     I6 = I7;\
	     L6 = L7;");

	/*Configuring the SPU secureP registers for boot peripheral to do secure access to memory*/
	*pREG_SPU0_SECUREP103 = 0x3; /*SPI2*/
	*pREG_SPU0_SECUREP146 = 0x3; /*MDMA0_SRC*/
	*pREG_SPU0_SECUREP147 = 0x3; /*MDMA0_DST*/

	/*Boot Command*/
	gBootCmd = 0;
	gBootCmd = 	(7 << BITP_ROM_BCMD_DEVICE) | /*SPI XIP Boot Mode*/
				(0 << BITP_ROM_BCMD_HOST) | /*master boot*/
				(0 << BITP_ROM_BCMD_NOCFG) | /*full peripheral configuration*/
				(0 << BITP_ROM_BCMD_NOAUTO) | /*enable auto device detection*/
				(2 << BITP_ROM_BCMD_DEVENUM) | /*SPI2*/
				(0 << BITP_ROM_BCMD_CHANNEL) | /*SPI2 channel 0*/
				(0 << 15) | /*2159x cannot set to 1*/
				(9 << BITP_ROM_BCMD_BCODE) | /*bcode, Single bit command , Quad bit address and data*/
				(0 << BITP_ROM_BCMD_SPIM_ADDR) | /*Flash address mode: use auto detection setting*/
				(0 << BITP_ROM_BCMD_SPIM_DUMMY) | /*Flash dummy cycle number: use auto detection setting*/
				(0 << BITP_ROM_BCMD_SPIM_SPEED); /*fast flash speed*/

	/* ROM API Call which can be invoked based on some conditions */
	adi_rom_Boot((unsigned int *)gApplicationPhysicalStartAddress, BITM_ROM_BFLAG_HOOK, 0, &ROM_BOOT_HOOK_FUNC1, gBootCmd);
}

Thanks and looking for your reply.

  • Hi,

    When calling the boot API you bypass all the preboot code that sets up all the C environment for the processor etc. We would recommend trying to undo all the configuration performed by the default startup code before calling the boot API. The startup code may expect items like caches and interrupts to be in certain states before being run for a second time.

    1. Make sure that SPU and SMPU configurations are not modified such that ROM cannot access the memory anymore.2. Make sure no interrupts are are still enabled and active, else when you call the new startup and install the default empty error handlers you will vector off to them
    3. Make sure caches for L1 and L2 are all disabled and flushed if applicable BEFORE calling the boot API and reset the BTB. You could be booting in the content via DMA but if caches enabled the core read on the startup could be taking stale data from the previously loaded application.
    4. Finally try setting the stack back to the same location to the boot ROM as documented in the processors boot chapter

    Regards,
    Divya.P

  • Thanks Divya.P, that's all make sense.

    In my case, all caches are already disabled in SSL and application projects. And I will carefully uninstall all interrupts and uninit all configured parts in SSL, then set the stack pointer to default just like the example SSL project does.

    thanks again.