We are using ADSP-21583 processor in our application.
In our custom board we have hardware interrupt connected to GPIO. We are able to assign ISR to this interrupt and it is executing correctly. This interrupt is the highest priority interrupt in our system.
We have another software interrupt assigned to Software 0 Interrupt Latch (IRPTL[28]). We are able to assign ISR to this interrupt also and it is executing correctly.
We are writing 32 bit value to SMC bus in software interrupt. The 32 bit value is transferred through SMC bus as two 16 bit transfers.
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unsigned int *var_ptr = (unsigned int *)0x4C000000; // SMC0 address
*var_ptr = 0xaaaaaaaa;
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My question is, suppose if hardware interrupt is received in between the two 16 bit SMC transfers, what will be the behavior of code execution?
Does the execution of hardware ISR happen after completing the two 16 bit SMC transfers? Or will the behavior be different?
