Post Go back to editing

ADSP21569 Multichannel (TDM) Mode problem

SPORT0A configure as 8 Multichannel (TDM) Mode RX,external clock and external frame sync,
SPORT0B configure as 8 Multichannel (TDM) Mode TX,external clock and external frame sync,when external clock is 12.288M and fs clock is 48K,SPORT0A and SPORT0B work fine,
but when external clock is 24.576M and fs clock is 96K,there is no interrupt in SPORT0ACallback,What could be the problem?

SPORT0A and SPORT0B's configuration as attach.

/**********************************************************************************************
* SPORT 0A
**********************************************************************************************/

/*!SPORT0A Instance*/
#define ADI_SPORT0A_INSTANCE 1

/*! Selects the Data Type Formatting for Half-Sport's Data transfer.
* Configurable for DSP serial mode/Multi-channel(TDM)/Packed I2S mode.
* Configured as :
* 0 : Right-justify data, zero-fill unused MSBs
* 1 : Right-justify data, sign-extend unused MSBs
* 2 : u-law compand data
* 3 : A-law compand data*/
#define ADI_SPORT0A_CTL_DTYPE 0ul
/*! Selects whether the Half-SPORT transmits or receives data LSB first or MSB first.
* Configurable for DSP serial mode/Multi-channel(TDM)/Packed I2S mode.
* Configured as
* 0 : MSB first sent/received (big endian)
* 1 : LSB first sent/received (little endian)*/
#define ADI_SPORT0A_CTL_LSBF 0ul
/*! Enables the half SPORT to perform 16- to 32-bit packing on received data
* and to perform 32- to 16-bit unpacking on transmitted data.
* Configured as :
* 0 : Disable
* 1 : Enable */
#define ADI_SPORT0A_CTL_PACK 0ul
/*! Enables the Half-SPORT (if SPORT_CTL.OPMODE =1) to transfer data in right-justified operation mode.
* Configured as :
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0A_CTL_RJUST 0ul
/*! Selects word length in bits for the Half-SPORT's data transfers.
* SLEN = (serial word length in bits) - 1 */
#define ADI_SPORT0A_CTL_SLEN 31ul
/*! DMA MSIZE will be selected/generated on the the basis of word lenght(slen).
* The MSIZE is selected as follows:
* for (slen <= 7 bits) -----> MSIZE = 1 Byte.
* for (slen <= 15 bits) -----> MSIZE = 2 Bytes.
* for (slen <= 15 bits) and (DMA packing is enebled) -----> MSIZE = 4 Bytes.
* for (slen <= 31 bits) -----> MSIZE = 4 Bytes.
* */
#define ADI_SPORT0A_DMA_MSIZE ENUM_DMA_CFG_MSIZE04
/*! DMA PSIZE will be selected/generated on the the basis of word lenght(slen).
* The PSIZE is selected as follows:
* for (slen <= 7 bits) -----> PSIZE = 1 Byte.
* for (slen <= 15 bits) -----> PSIZE = 2 Bytes.
* for (slen <= 15 bits) and (DMA packing is enebled) -----> PSIZE = 4 Bytes.
* for (slen <= 31 bits) -----> PSIZE = 4 Bytes.
* */
#define ADI_SPORT0A_DMA_PSIZE ENUM_DMA_CFG_PSIZE04

/*! Selects whether the Half-SPORT uses an internal or external clock.
* Configured as :
* 0 : External clock
* 1 : Internal clock*/
#define ADI_SPORT0A_CTL_ICLK 0ul
/*! Selects the rising or falling edge of the SPORT_CLK for the Half-SPORT to sample received data and frame sync.
* Configured as:
* 0 : Clock falling edge
* 1 : Clock rising edge*/
#define ADI_SPORT0A_CTL_CKRE 1ul
/*! Enables gated clock operation for the Half-SPORT.
* Configurable for DSP serial mode or left-justified stereo modes.
* This bit is ignored when the half SPORT is in right-justified mode or multichannel mode
* Configured as :
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0A_CTL_GCLKEN 0ul
/*! Selects whether or not the Half-SPORT requires frame sync for data transfer.
* Configurable only for DSP serial mode. For all other modes this bit is set automatically.
* Configured as :
* 0 : No frame sync required
* 1 : Frame sync required*/
#define ADI_SPORT0A_CTL_FSR 0ul
/*! Selects whether the Half-SPORT uses an internal frame sync or uses an external frame sync.
* Configured as :
* 0 : External frame sync
* 1 : Internal frame sync*/
#define ADI_SPORT0A_CTL_IFS 0ul
/*! Selects whether the Half-SPORT uses a data-independent or data-dependent frame sync.
* Configurable for DSP Serial/I2S/Left Justified/Right justified mode.
* Configured as :
* 0 : Data-dependent frame sync
* 1 : Data-independent frame sync*/
#define ADI_SPORT0A_CTL_DIFS 0ul
/*! When the Half-SPORT is in DSP standard mode and multichannel mode,
* the LFS bit selects whether the Half SPORT uses active low or active high frame sync.
* When the half SPORT is in I2S / packed / left-justified mode,
* the LFS bit acts as L_FIRST, selecting whether the half SPORT transfers data first for the left or right channel.
* Configured as :
* 0 : Active high frame sync (DSP standard mode) or rising
* edge frame sync (multichannel mode)
* or right channel first (I2S/packed mode)
* or left channel first (left-justified mode)
* 1 : Active low frame sync (DSP standard mode) or falling
* edge frame sync (multichannel mode)
* or left channel first (I2S/packed mode)
* or right channel first (left-justified mode)*/
#define ADI_SPORT0A_CTL_LFS 0ul
/*! When the Half-SPORT is in DSP standard mode or in right-justified mode,
* the LAFS bit selects whether the half SPORT generates a late frame sync or generates an early frame sync signal.
* When the Half-SPORT is in I2S / left-justified mode, the LAFS bit acts as OPMODE2,
* selecting whether the Half-SPORT is in left-justified mode or I2S mode.
* When the Half-SPORT is in multichannel mode, the LAFS bit is reserved.
* Configured as:
* 0 : Early frame sync (or I2S mode)
* 1 : Late frame sync (or left-justified mode)*/
#define ADI_SPORT0A_CTL_LAFS 0ul
/*! Enables the Half-SPORT to start transmitting or receiving after detecting an active edge of an external frame sync.
* Configurable for DSP Serial/Multi-channel(TDM) mode.
* Configured as:
* 0 : Level detect frame sync
* 1 : Edge detect frame sync*/
#define ADI_SPORT0A_CTL_FSED 0ul
/*! Selects whether the half SPORT operates in DSP standard/multichannel mode or operates in I2S/packed/left-justified mode.
* Configured as :
* 0 : DSP Serial/Multi-channel(TDM) mode
* 1 : I2S/packed/left-justified/Right Justified mode */
#define ADI_SPORT0A_CTL_OPMODE 0ul
/*! Selects the transfer direction (receive or transmit)for the half SPORT's primary and secondary channels.
* Configured as :
* 0 : Receive
* 1 : Transmit */
#define ADI_SPORT0A_CTL_SPTRAN 0ul


/*! Specifies the SPORT0A_Control register Configuration*/
#define ADI_SPORT_0A_CTL ((ADI_SPORT0A_CTL_DTYPE<<BITP_SPORT_CTL_A_DTYPE)|(ADI_SPORT0A_CTL_LSBF<<BITP_SPORT_CTL_A_LSBF)|(ADI_SPORT0A_CTL_SLEN<<BITP_SPORT_CTL_A_SLEN)|(ADI_SPORT0A_CTL_PACK<<BITP_SPORT_CTL_A_PACK)|(ADI_SPORT0A_CTL_ICLK<<BITP_SPORT_CTL_A_ICLK)|(ADI_SPORT0A_CTL_OPMODE<<BITP_SPORT_CTL_A_OPMODE)|(ADI_SPORT0A_CTL_CKRE<<BITP_SPORT_CTL_A_CKRE)|(ADI_SPORT0A_CTL_FSR<<BITP_SPORT_CTL_A_FSR)|(ADI_SPORT0A_CTL_IFS<<BITP_SPORT_CTL_A_IFS)|(ADI_SPORT0A_CTL_DIFS<<BITP_SPORT_CTL_A_DIFS)|(ADI_SPORT0A_CTL_LFS<<BITP_SPORT_CTL_A_LFS)|(ADI_SPORT0A_CTL_LAFS<<BITP_SPORT_CTL_A_LAFS)|(ADI_SPORT0A_CTL_RJUST<<BITP_SPORT_CTL_A_RJUST)|(ADI_SPORT0A_CTL_FSED<<BITP_SPORT_CTL_A_FSED)|(ADI_SPORT0A_CTL_GCLKEN<<BITP_SPORT_CTL_A_GCLKEN)|(ADI_SPORT0A_CTL_SPTRAN<<BITP_SPORT_CTL_A_SPTRAN))


/*! Select the clock divisor that the Half-SPORT uses to calculate the sport clock from the processor system clock.
* CLKDIV = ( SCLK / SPORT_ACLK) - 1 */
#define ADI_SPORT0A_DIV_CLKDIV 0ul
/*! Select the number of transmit or receive clock cycles that the Half-SPORT counts before generating a frame sync pulse.
* FSDIV = (SPORT_ACLK / SPORT_AFS) - 1 */
#define ADI_SPORT0A_DIV_FSDIV 31ul


/*! Specifies the SPORT0A_Divisor register Configuration*/
#define ADI_SPORT_0A_DIV ((ADI_SPORT0A_DIV_CLKDIV<<BITP_SPORT_DIV_A_CLKDIV)|(ADI_SPORT0A_DIV_FSDIV<<BITP_SPORT_DIV_A_FSDIV))


/*! Multi-Channel (TDM) Mode : Selects the start location for the Half-SPORT's active window of channels within the 1024-channel range.
* For Right Justified Mode : The least significant 6 bits of WOFFSET serve as the delay count (DCNT) field*/
#define ADI_SPORT0A_MCTL_WOFFSET 0x00ul
/*! Selects the window size for the Half-SPORT's active window of channels.
* WSIZE = (number of channel slots) -1 */
#define ADI_SPORT0A_MCTL_WSIZE 0x07ul
/*! Selects the delay (in serial clock cycles) between the Half-SPORT's multichannel frame sync pulse and channel 0 */
#define ADI_SPORT0A_MCTL_MFD 0x00ul
/*! Enables DMA data packing for transmit and enables DMA data unpacking for the Half-SPORT's multichannel data transfers.
* Configured as:
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0A_MCTL_MCPDE 0x01ul
/*! Enables multichannel operations for the Half-SPORT.
* * Configured as:
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0A_MCTL_MCE 0x01ul


/*! Specifies the SPORT0A_Multichannel Control register Configuration*/
#define ADI_SPORT_0A_MCTL ((ADI_SPORT0A_MCTL_MCE<<BITP_SPORT_MCTL_A_MCE)|(ADI_SPORT0A_MCTL_MCPDE<<BITP_SPORT_MCTL_A_MCPDE)|(ADI_SPORT0A_MCTL_MFD<<BITP_SPORT_MCTL_A_MFD)|(ADI_SPORT0A_MCTL_WSIZE<<BITP_SPORT_MCTL_A_WSIZE)|(ADI_SPORT0A_MCTL_WOFFSET<<BITP_SPORT_MCTL_A_WOFFSET))


/*! Specifies the SPORT0A Channel Select 0 register Configuration*/
#define ADI_SPORT_0A_CS0 0xfful
/*! Specifies the SPORT0A Channel Select 1 register Configuration*/
#define ADI_SPORT_0A_CS1 0x00ul
/*! Specifies the SPORT0A Channel Select 2 register Configuration*/
#define ADI_SPORT_0A_CS2 0x00ul
/*! Specifies the SPORT0A Channel Select 3 register Configuration*/
#define ADI_SPORT_0A_CS3 0x00ul

/**********************************************************************************************
* SPORT 0B
**********************************************************************************************/
/* SPORT0B Instance*/
#define ADI_SPORT0B_INSTANCE 1

/* Selects the Data Type Formatting for Half-Sport's Data transfer.
* Configurable for DSP serial mode/Multi-channel(TDM)/Packed I2S mode.
* Configured as :
* 0 : Right-justify data, zero-fill unused MSBs
* 1 : Right-justify data, sign-extend unused MSBs
* 2 : u-law compand data
* 3 : A-law compand data*/
#define ADI_SPORT0B_CTL_DTYPE 0ul
/* Selects whether the Half-SPORT transmits or receives data LSB first or MSB first.
* Configurable for DSP serial mode/Multi-channel(TDM)/Packed I2S mode.
* Configured as
* 0 : MSB first sent/received (big endian)
* 1 : LSB first sent/received (little endian)*/
#define ADI_SPORT0B_CTL_LSBF 0ul
/* Enables the half SPORT to perform 16- to 32-bit packing on received data
* and to perform 32- to 16-bit unpacking on transmitted data.
* Configured as :
* 0 : Disable
* 1 : Enable */
#define ADI_SPORT0B_CTL_PACK 0ul
/* Enables the Half-SPORT (if SPORT_CTL.OPMODE =1) to transfer data in right-justified operation mode.
* Configured as :
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0B_CTL_RJUST 0ul
/* Selects word length in bits for the Half-SPORT's data transfers.
* SLEN = (serial word length in bits) - 1 */
#define ADI_SPORT0B_CTL_SLEN 31ul

/* DMA MSIZE will be selected/generated on the the basis of word lenght(slen).
* The MSIZE is selected as follows:
* for (slen <= 7 bits) -----> MSIZE = 1 Byte.
* for (slen <= 15 bits) -----> MSIZE = 2 Bytes.
* for (slen <= 15 bits) and (DMA packing is enebled) -----> MSIZE = 4 Bytes.
* for (slen <= 31 bits) -----> MSIZE = 4 Bytes.
* */
#define ADI_SPORT0B_DMA_MSIZE ENUM_DMA_CFG_MSIZE04
/* DMA PSIZE will be selected/generated on the the basis of word lenght(slen).
* The PSIZE is selected as follows:
* for (slen <= 7 bits) -----> PSIZE = 1 Byte.
* for (slen <= 15 bits) -----> PSIZE = 2 Bytes.
* for (slen <= 15 bits) and (DMA packing is enebled) -----> PSIZE = 4 Bytes.
* for (slen <= 31 bits) -----> PSIZE = 4 Bytes.
* */
#define ADI_SPORT0B_DMA_PSIZE ENUM_DMA_CFG_PSIZE04

/* Selects whether the Half-SPORT uses an internal or external clock.
* Configured as :
* 0 : External clock
* 1 : Internal clock*/
#define ADI_SPORT0B_CTL_ICLK 0ul
/* Selects the rising or falling edge of the SPORT_CLK for the Half-SPORT to sample received data and frame sync.
* Configured as:
* 0 : Clock falling edge
* 1 : Clock rising edge */
#define ADI_SPORT0B_CTL_CKRE 1ul
/* Enables gated clock operation for the Half-SPORT.
* Configurable for DSP serial mode or left-justified stereo modes.
* This bit is ignored when the half SPORT is in right-justified mode or multichannel mode
* Configured as :
* 0 : Disable
* 1 : Enable */
#define ADI_SPORT0B_CTL_GCLKEN 0ul
/* Selects whether or not the Half-SPORT requires frame sync for data transfer.
* Configurable only for DSP serial mode. For all other modes this bit is set automatically.
* Configured as :
* 0 : No frame sync required
* 1 : Frame sync required */
#define ADI_SPORT0B_CTL_FSR 0ul
/* Selects whether the Half-SPORT uses an internal frame sync or uses an external frame sync.
* Configured as :
* 0 : External frame sync
* 1 : Internal frame sync*/
#define ADI_SPORT0B_CTL_IFS 0ul
/* Selects whether the Half-SPORT uses a data-independent or data-dependent frame sync.
* Configurable for DSP Serial/I2S/Left Justified/Right justified mode.
* Configured as :
* 0 : Data-dependent frame sync
* 1 : Data-independent frame sync*/
#define ADI_SPORT0B_CTL_DIFS 0ul
/* When the Half-SPORT is in DSP standard mode and multichannel mode,
* the LFS bit selects whether the Half SPORT uses active low or active high frame sync.
* When the half SPORT is in I2S / packed / left-justified mode,
* the LFS bit acts as L_FIRST, selecting whether the half SPORT transfers data first for the left or right channel.
* Configured as :
* 0 : Active high frame sync (DSP standard mode) or rising
* edge frame sync (multichannel mode)
* or right channel first (I2S/packed mode)
* or left channel first (left-justified mode)
* 1 : Active low frame sync (DSP standard mode) or falling
* edge frame sync (multichannel mode)
* or left channel first (I2S/packed mode)
* or right channel first (left-justified mode)*/
#define ADI_SPORT0B_CTL_LFS 0ul
/* When the Half-SPORT is in DSP standard mode or in right-justified mode,
* the LAFS bit selects whether the half SPORT generates a late frame sync or generates an early frame sync signal.
* When the Half-SPORT is in I2S / left-justified mode, the LAFS bit acts as OPMODE2,
* selecting whether the Half-SPORT is in left-justified mode or I2S mode.
* When the Half-SPORT is in multichannel mode, the LAFS bit is reserved.
* Configured as:
* 0 : Early frame sync (or I2S mode)
* 1 : Late frame sync (or left-justified mode)*/
#define ADI_SPORT0B_CTL_LAFS 0ul
/* Enables the Half-SPORT to start transmitting or receiving after detecting an active edge of an external frame sync.
* Configurable for DSP Serial/Multi-channel(TDM) mode.
* Configured as:
* 0 : Level detect frame sync
* 1 : Edge detect frame sync*/
#define ADI_SPORT0B_CTL_FSED 0ul
/* Selects whether the half SPORT operates in DSP standard/multichannel mode or operates in I2S/packed/left-justified mode.
* Configured as :
* 0 : DSP Serial/Multi-channel(TDM) mode
* 1 : I2S/packed/left-justified/Right Justified mode */
#define ADI_SPORT0B_CTL_OPMODE 0ul
/* Selects the transfer direction (receive or transmit)for the half SPORT's primary and secondary channels.
* Configured as :
* 0 : Receive
* 1 : Transmit */
#define ADI_SPORT0B_CTL_SPTRAN 1ul

/* Specifies the SPORT_0B_Control register Configuration*/
#define ADI_SPORT_0B_CTL ((ADI_SPORT0B_CTL_DTYPE<<BITP_SPORT_CTL_B_DTYPE)|(ADI_SPORT0B_CTL_LSBF<<BITP_SPORT_CTL_B_LSBF)|(ADI_SPORT0B_CTL_SLEN<<BITP_SPORT_CTL_B_SLEN)|(ADI_SPORT0B_CTL_PACK<<BITP_SPORT_CTL_B_PACK)|(ADI_SPORT0B_CTL_ICLK<<BITP_SPORT_CTL_B_ICLK)|(ADI_SPORT0B_CTL_OPMODE<<BITP_SPORT_CTL_B_OPMODE)|(ADI_SPORT0B_CTL_CKRE<<BITP_SPORT_CTL_B_CKRE)|(ADI_SPORT0B_CTL_FSR<<BITP_SPORT_CTL_B_FSR)|(ADI_SPORT0B_CTL_IFS<<BITP_SPORT_CTL_B_IFS)|(ADI_SPORT0B_CTL_DIFS<<BITP_SPORT_CTL_B_DIFS)|(ADI_SPORT0B_CTL_LFS<<BITP_SPORT_CTL_B_LFS)|(ADI_SPORT0B_CTL_LAFS<<BITP_SPORT_CTL_B_LAFS)|(ADI_SPORT0B_CTL_RJUST<<BITP_SPORT_CTL_B_RJUST)|(ADI_SPORT0B_CTL_FSED<<BITP_SPORT_CTL_B_FSED)|(ADI_SPORT0B_CTL_GCLKEN<<BITP_SPORT_CTL_B_GCLKEN)|(ADI_SPORT0B_CTL_SPTRAN<<BITP_SPORT_CTL_B_SPTRAN))


/* Select the clock divisor that the Half-SPORT uses to calculate the sport clock from the processor system clock.
* CLKDIV = ( SCLK / SPORT_ACLK) - 1 */
#define ADI_SPORT0B_DIV_CLKDIV 0ul
/* Select the number of transmit or receive clock cycles that the Half-SPORT counts before generating a frame sync pulse.
* FSDIV = (SPORT_ACLK / SPORT_AFS) - 1 */
#define ADI_SPORT0B_DIV_FSDIV 31ul

/* Specifies the SPORT0B_Divisor register Configuration*/
#define ADI_SPORT_0B_DIV ((ADI_SPORT0B_DIV_CLKDIV<<BITP_SPORT_DIV_B_CLKDIV)|(ADI_SPORT0B_DIV_FSDIV<<BITP_SPORT_DIV_B_FSDIV))


/* Multi-Channel (TDM) Mode : Selects the start location for the Half-SPORT's active window of channels within the 1024-channel range.
* For Right Justified Mode : The least significant 6 bits of WOFFSET serve as the delay count (DCNT) field*/
#define ADI_SPORT0B_MCTL_WOFFSET 0x00ul
/* Selects the window size for the Half-SPORT's active window of channels.
* WSIZE = (number of channel slots) -1 */
#define ADI_SPORT0B_MCTL_WSIZE 0x07ul
/* Selects the delay (in serial clock cycles) between the Half-SPORT's multichannel frame sync pulse and channel 0 */
#define ADI_SPORT0B_MCTL_MFD 0x00ul
/* Enables DMA data packing for transmit and enables DMA data unpacking for the Half-SPORT's multichannel data transfers.
* Configured as:
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0B_MCTL_MCPDE 0x01ul
/* Enables multichannel operations for the Half-SPORT.
* * Configured as:
* 0 : Disable
* 1 : Enable*/
#define ADI_SPORT0B_MCTL_MCE 0x01ul

/* Specifies the SPORT0B_Multichannel Control register Configuration*/
#define ADI_SPORT_0B_MCTL ((ADI_SPORT0B_MCTL_MCE<<BITP_SPORT_MCTL_B_MCE)|(ADI_SPORT0B_MCTL_MCPDE<<BITP_SPORT_MCTL_B_MCPDE)|(ADI_SPORT0B_MCTL_MFD<<BITP_SPORT_MCTL_B_MFD)|(ADI_SPORT0B_MCTL_WSIZE<<BITP_SPORT_MCTL_B_WSIZE)|(ADI_SPORT0B_MCTL_WOFFSET<<BITP_SPORT_MCTL_B_WOFFSET))

/* Specifies the SPORT0B Channel Select 0 register Configuration*/
#define ADI_SPORT_0B_CS0 0xfful
/* Specifies the SPORT0B Channel Select 1 register Configuration*/
#define ADI_SPORT_0B_CS1 0x00ul
/* Specifies the SPORT0B Channel Select 2 register Configuration*/
#define ADI_SPORT_0B_CS2 0x00ul
/* Specifies the SPORT0B Channel Select 3 register Configuration*/
#define ADI_SPORT_0B_CS3 0x00ul