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Enabling Timer0 Interrupt for ARM Core on SC587

Category: Software
Product Number: SC587
Software Version: CCES 2.8.0

I am trying to configure Timer0 as a periodic interrupt received on the ARM core.  When using the ADI Timer API, things work as expected and I receive calls to my ISR as expected.  However, due to code size issues, I want to enable this same functionality without using the ADI Timer API.  Despite my best attempts, I cannot ever receive the interrupt in the ARM core, and never see my ISR get called. 

The following code illustrates what works properly using the Timer API vs. what I'm trying to do using just register access to configure the timer.  I can see the timer is running just fine using register access to configure, but the interrupt never makes it to the ARM core for processing.  

#if USING_TIMER_API    //This way works

    eTmrResult = adi_tmr_Open     (FAST_TMR,         // Timer Number
                                                                       FastTimerMemory,  // Pointer to Timer Management Memory Location
                                                                       ADI_TMR_MEMORY,   // Size of allocated Management Memory Location
                                                                      FastTimerISR,     // Pointer to Timer ISR
                                                                       NULL,             // Optional pointer to callback parameter to be passed to ISR.
                                                                       &hFastTimer       // Pointer to storage for Handle to the opened timer.

    *pREG_TIMER0_TMR0_CFG = 0x43C;                       // Continuous PWM, SCLK0, Period Expire, Output Disable.
    *pREG_TIMER0_TMR0_PER = FAST_TMR_PER;                // Set the period.
    *pREG_TIMER0_RUN_SET |= BITM_TIMER_RUN_SET_TMR00;    // Enable Timer0 using BIT0.

#else     / /Interrupt never happens using this code

    gicResult = adi_gic_Enable(true);
    gicResult = adi_int_InstallHandler(INTR_TIMER0_TMR0 /*26*/,&FastTimerISR,0,false);
    gicResult = adi_gic_SetTargetCore(INTR_TIMER0_TMR0/*26*/,ADI_GIC_CORE_0);
    gicResult = adi_gic_EnableInt(INTR_TIMER0_TMR0,true);

    *pREG_SEC0_GCTL |= ENUM_SEC_GCTL_EN;      // Enable SEC
    *pREG_SEC0_SCTL26 |= 0x03;                                      // Configure TImer0 Interrupt

    *pREG_TIMER0_TMR0_CFG = 0x043C; // Continuous PWM, SCLK0, Period Expire, Output Disable.
    *pREG_TIMER0_TMR0_PER = FAST_TMR_PER;    // Set Period.

    *pREG_TIMER0_DATA_ILAT |= BITM_TIMER_DATA_ILAT_TMR00;   // Clear any previous latched interrupt.
    *pREG_TIMER0_RUN_SET |= BITM_TIMER_RUN_SET_TMR00;      // Enable Timer0 via BIT0.

Please help me understand what I need to do differently to get the Timer0 interrupt processed by the ARM core of my SC587.

  • Hi ,

    adi_int_InstallHandler() API can be used to install an interrupt handler for a given processor interrupt. The API takes the following arguments:(iid, pfHandler, pCBParam,bEnable)

    bEnable - Flag, which indicates whether to enable or disable the given interrupt, after the interrupt handler installation. This argument should be set to
    • true to enable the interrupt
    • false to disable the interrupt

    So, please set 1 or true to bEnable argument to activate the interrupt and let us know the response.

    Also, please refer the attached code for your


  • Thanks for your response.  The code actually had 2 issues.  First, when using the ADI Timer API, I didn't see the allow during emulation bit being set in the TMR0_CFG register -- reading that value after the timer was up and running did not show the bit set.  However, I am using an ICE-1000, so that apparently requires the run during emulation bit to be set when using register access to configure the timer.  Second, when using adi_int_installHandler, I needed to pass the same value in pCBParam as the ADI Timer API uses to indicate the period expired to the ISR.  Fixing both those problems has allowed me to configure the timer and correctly receive the period interrupts in the ARM core.  Thanks!