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Is it possible to use SPDIF in "slave" clock mode on the SC587 ?

Category: Hardware
Product Number: SC587

The silicon anomaly list for the SC587 describes an anomaly with the SPDIF receiver : 

73. 20000094 - SPDIF Receiver Output Clock Is Unreliable:
When operating properly, the SPDIF receiver output clock (SPDIF_RX_TDMCLK_O) frequency is 256 times the sampling rate. The SPDIF
receiver, however, fails to maintain this relationship; thus, the SPDIF_RX_TDMCLK_O output clock is unreliable.

Do not use the SPDIF_RX_TDMCLK_O output clock.

1.0, 1.2

Does that mean I effectively can't use the SPDIF to receive a signal from an externally clocked device ? Ie recovering a clock from the SPDIF Rx stream ?

  • I suspect the answer is : you have to use an ASRC like shown in the spdif_playback example project ? 

                 _____________                  _____________                  _____________
                |             |---Data0------->|             |---Data0------->|             |
                |             |---Clk--------->|   ASRC0     |<--Clk---x----->|             |
     DAI019---->|             |---Fs---------->|_____________|<--Fs----|--x-->|             |
                |  Rx SPDIF   |                                        |  |   |    SPORT    |
                |             |                                        |  |   |     0a      |
                |             |                                        |  |   |             |
                |_____________|                                        |  |   |_____________|
                                               _____________           |  |         |
                                  DAI103      |   3.072 MHz |----------x  |         |
                                25.476MHz -x->|PCGA   48kHz |-------------x     Mem Copy
                                              |_____________|                       |
                                                _____________                  _____v_______
                                               |             |<--Data0--------|             |
                                               |             |---Clk--------->|             |
                                               |             |---Fs---------->|             |
                                               |  AD1962a    |                |    SPORT    |
                                               |    DAC      |                |     4b      |
                                               |             |                |             |
                                               |_____________|                |_____________|

  • Hi Rob,

    We understood you to use the SPDIF as slave while using it, SPDIF cannot receive clk from external device. The S/PDIF receiver recovers the clock that generated the AES3/SPDIF biphase encoded stream from the incoming

    S/PDIF stream. This clock is used by the receiver to clock in the biphase encoded data stream and also to provide clocks for either the SPORTs, sample rate converter, or the AES3 and S/PDIF transmitter. Kindly refer the below blcok image of SPDIF receiver.



  • Yes, what I meant was - I can't use the clock recovered from SPDIF as an MCLK for the rest of my system, ie using the SPDIF as the "clock source" in the system so users who wanted to connect over SPDIF to the device would be forced to use the device as the clock source for their SPDIF interface. 

  • Hi,

    If you are asking about connecting SPDIFx_RX_CLK_O to other devices. Then it is possible. Please refer "Table 22-6: DAI0 Routing Capabilities" for the different routing capabilities for the DAI unit in the below linked HRM: 

    For your reference, in the SPDIF_Loopback example using SRU routing SPDIF0_RX_CLK_O is connected to SPORT BCLK.


  • Right, so there's a BCLK at 64FS but no 256FS that would be suitable for use as a system MCLK, thanks. 

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