SECI event trigger with external PINT interrupts.

import "asm_sprt.h";
.import "hwInt_Core1.h"; 

.global _KHz30Int; 
.type _smcTest,STT_FUNC; 

.section/pm seg_pmco;


_KHz30Int: 
	entry: 
	
	//1. Write to the SEC_GCTL register to enable the SEC.
	r0= 0x00000000; 
	dm(SEC0_GCTL) = r0;
	
	//2. Write to the appropriate SCI SEC_CCTL[n] register to enable SEC interrupts to be sent to that core.(P-7-25 )
	/*
	LOCK | NMIEN | WFI | RESET | EN
	---- | - 	 | ----| -     | ---
	31   | 16    | 12  | 1     | 0
	
	*/
	r0=0x00010001;
	dm(SEC0_CCTL1)= r0; 
	
	
	//3. Write to the appropriate SSI SEC_SCTL[n] register to enable that peripheral as an interrupt source and to
	//set the core target field to map the source to the desired SCI.
			r0=0x00010001;
	dm(SEC0_SCTL40)= r0; 
	
	//Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling
	//Interrupt handling within an individual core requires specific handshaking with the SEC to ensure
	//that nested interrupts are properly tracked and that new peripheral interrupts being raised within the SEC
	//are either passed immediately to the core or held off and queued within the SEC for later servicing. Inside the SEC ISR, the following steps
	//are required:
	//Use this procedure to write a custom dispatcher inside the Interrupt Service Routine. Note that the core needs to
	//read the SEC_CSID[n] register and acknowledge it by writing the same value. It should also write to the
	//SEC_END register after the ISR execution completes.
	//1. Read the SEC_CSID[n] register to obtain the source ID of the peripheral interrupt request.
	
	ustat1 =dm(SEC0_CSID1); /* Source Interrupt identifier (SID) from SEC */
	
	//2. Write the read value back to the SEC_CSID[n] register to send the acknowledge signal to the SEC that the
	//core has accepted and begun processing for the interrupt request.
		dm(SEC0_CSID1)=ustat1; /* Acknowledge */
	//3. Execute the actual ISR (typically a call to a specific handler function from a look-up table based on the peripheral source ID). 
	//Write to the SEC_GCTL register to enable the SEC.

	r0 = SEC0_GCTL; 
	r0= bset r0 by en_SEC;
	JUMP _KHz30Int;  
	//4. Write the SEC_CSID[n] of the active interrupt (read in step 1 above) to the SEC_END register to signal to
	//the SEC that the interrupt has now been serviced.
	dm(SEC0_END) = ustat1; 
	rti;  //5. Return from interrupt
	
	
	
	// set PD_03 as input pin and register ISR TO EVT and IVG
	
	r0= PORTD_FER_SET
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	
	r0= PORTD_INEN_SET
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	
	r0= PORTD_DIR_CLR
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	
	r0= PORTD_INEN_SET
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	
	r0= 00000001; 
	dm(PINT2_ASSIGN)=r0; // mux PDL to B0
	
	ro= PINT2_EDGE_SET; 
	r0= bset r0 by interrupt0_pos; 

exit; 
_KHz30Int.END; 
.endseg;