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SECI event trigger with external PINT interrupts.

Category: Software
Product Number: adsp-21583
Software Version: cces 2.11.1

hi team

we are porting from ADSP21161 SHARC to ADSP-21583 SHARC + processor. 

the SHARC+ processor ADSP 21583 does not have external interrupts. it has one single SECI for addressing all the interrupt sources. 

Page: 4-69 PRM 

i have an external hardware interrupt from GPIO port D  and then after 4 external interrupts i need to get 1 software interrupt. 

I have programmed it untill Figure 14-5 GPIO programming model from HRM 

but do not get where to do the steps highlighted in GPIO programming from point B in below flow chart. 

 as i could not find what the function __dispatcher_SEC (db) is doing. i have made a custom entry in the app.ivt and called  _KHz30Int(DB)  , the file is attached here

could i get a sample code for SECI even triggering , registering and ISR example for external hardware and software interrupts ? 

import "asm_sprt.h";
.import "hwInt_Core1.h"; 

.global _KHz30Int; 
.type _smcTest,STT_FUNC; 

.section/pm seg_pmco;

	//1. Write to the SEC_GCTL register to enable the SEC.
	r0= 0x00000000; 
	dm(SEC0_GCTL) = r0;
	//2. Write to the appropriate SCI SEC_CCTL[n] register to enable SEC interrupts to be sent to that core.(P-7-25 )
	---- | - 	 | ----| -     | ---
	31   | 16    | 12  | 1     | 0
	dm(SEC0_CCTL1)= r0; 
	//3. Write to the appropriate SSI SEC_SCTL[n] register to enable that peripheral as an interrupt source and to
	//set the core target field to map the source to the desired SCI.
	dm(SEC0_SCTL40)= r0; 
	//Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling
	//Interrupt handling within an individual core requires specific handshaking with the SEC to ensure
	//that nested interrupts are properly tracked and that new peripheral interrupts being raised within the SEC
	//are either passed immediately to the core or held off and queued within the SEC for later servicing. Inside the SEC ISR, the following steps
	//are required:
	//Use this procedure to write a custom dispatcher inside the Interrupt Service Routine. Note that the core needs to
	//read the SEC_CSID[n] register and acknowledge it by writing the same value. It should also write to the
	//SEC_END register after the ISR execution completes.
	//1. Read the SEC_CSID[n] register to obtain the source ID of the peripheral interrupt request.
	ustat1 =dm(SEC0_CSID1); /* Source Interrupt identifier (SID) from SEC */
	//2. Write the read value back to the SEC_CSID[n] register to send the acknowledge signal to the SEC that the
	//core has accepted and begun processing for the interrupt request.
		dm(SEC0_CSID1)=ustat1; /* Acknowledge */
	//3. Execute the actual ISR (typically a call to a specific handler function from a look-up table based on the peripheral source ID). 
	//Write to the SEC_GCTL register to enable the SEC.

	r0 = SEC0_GCTL; 
	r0= bset r0 by en_SEC;
	JUMP _KHz30Int;  
	//4. Write the SEC_CSID[n] of the active interrupt (read in step 1 above) to the SEC_END register to signal to
	//the SEC that the interrupt has now been serviced.
	dm(SEC0_END) = ustat1; 
	rti;  //5. Return from interrupt
	// set PD_03 as input pin and register ISR TO EVT and IVG
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	r0 = bset r0 by interrupt0_pos; // PD_03 is connected to interrupt 0 ; 
	r0= 00000001; 
	dm(PINT2_ASSIGN)=r0; // mux PDL to B0
	r0= bset r0 by interrupt0_pos; 


  • Hi,

    We have an ADSP-SC584 Pushbutton example code. Please find the attached code.
    Please take this as a reference and modify accordingly to your


  • hi 

    i tried with the code provided here. 

    I have an external hardware interrupt coming at portD pin 3 ... 

    and based on HRM i expect SEC ID = 41 to appear in the control registers

    but we get SID: 139 (8B) in the registers. please see the screenshot. 

    the header files use two words, one is core interrupt and system interrupt. what is difference between core and system interrupt ID  ?  looks like some different interrupt or SEC ID is getting registered. please assist in this. 

  • Hi ,

    To assist you better, can you please share your project which simulates this issue.

    We would suggest you to refer the PORT Interrupt Signals (Page No:579/3973) in ADSP-SC58x HRM using below link for more details about interrupt mapping:

    Regarding "The header files use two words, one is core interrupt and system interrupt. what is difference between core and system interrupt ID?"
    >>>Core interrupt : The processor has internally-generated interrupts for the timers, user-defined software interrupts and different levels for emulation support. Furthermore core exceptions as follows: circular buffer overflow, stack overflows, arithmetic fixed/floating-point exceptions, L1 parity error, illegal opcode error.
    There are 32 core interrupts supported by SHARC+ core. The various interrupts caused by external events on previous SHARC processors have been replaced by the single SECI interrupt. The relative priorities of the remaining interrupts are unchanged, except for CB7I. As the interrupt numbers are different the vector offsets are also changed from previous SHARC processors.

    Please refer "Interrupt Priority and Vector Table" in below linked PRM:

    >>>System Interrupt: The SHARC+ core uses the system bus infrastructure that appears on many processors from Analog Devices. In this bus architecture, external interrupts are managed by the system event controller (SEC). Like interrupt from GPIO, SPI, SPORT are system interrupts which is generated by external to the core.

    If porting code from previous SHARC processors, note that your code needs to be modified to interface with the SEC and to remove existing support for external interrupts.

    Also, you can refer the below mentioned CCES help path for more information about interrupt.
    CrossCore® Embedded Studio 2.11.0 > System Run-Time Documentation > Interrupt Support > Interrupt Support Specific to SHARC and SHARC+ Processors