mismatch in SMC timings for ADSP-SC584 EZ-KIT lite

Hi fellow Engineers,

I need to interface SRAM based FPGA through SMC interface to the ADSP-SC584 processor. I want to check the cycles taken to complete the read and write from SMC interface 

As per ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Rev 1.0 (HRM) >> page 11-8: >> Static memory Controller (SMC) section, Basic Asynchronous SRAM write followed by read, I programmed the parameters as mentioned in it. 

• RAT: 5  RHT: 1  RST: 3  WAT: 4  WHT: 2  WST: 2  Turnaround transition time = 2 cycles , Idle transition time = 0 cycles. 
• based on timing diagram as shown in the HRM it should take for READ:  9-SCLK_0 cycles and for WRITE:  10 SCLK_0  , where SCLK_0 (100MHZ) = 1/4 CCLK (=400 MHZ) 
• for cycles.h the required -DDO_CYCLE_COUNTS in compiler flags is added
• Evaluation board: ADSP-SC584-EZ-KIT-LITE

but the result of cycles taken are not matching with expected cycle counts from cycles.h basic cycle counting method. 

the observed cycles for READ: 130 , Write: 15 

here is the code i've used to get the SMC read and write cycle counts. Please assist in clarifying the correct cycle count and best way to program the SMC interface. 

 

Cortex -Core 0

#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <stdio.h>

int main()
{

adi_initComponents();
adi_core_enable(ADI_CORE_SHARC1);
return 0;
}

SHARC_core1

#include <builtins.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include <cycle_count.h>
#include <stdio.h>
#include <cycles.h>
#include <time.h> //for CLOCKS_PER_SEC
#include <sysreg.h>
#include <defSC584.h>
#include <platform_include.h>


void SetUncached(void);
void ConfigSMC(void);
#define CLOCKS_PER_SEC 400000000LL


int
main ()
{
cycle_t s, a, t, b;
volatile unsigned int foo;

adi_initComponents ();
ConfigSMC (); // setting the CTL, TIM, ETIM registers, uncached SMC memory

START_CYCLE_COUNT(s); // start the counter

foo = *(volatile unsigned int*) (0x40000000); //read from SMC start address

STOP_CYCLE_COUNT(t, s); // stop the counter
PRINT_CYCLES("\nRead = ", t);

return 0 ;
}


void SetUncached (void)
{
uint32_t cfg;

*pREG_SHL1C0_RANGE_START6 = 0x40000000; // SMC0 start address
*pREG_SHL1C0_RANGE_END6 = 0x43FFFFFF; // SMC0 End address
cfg = *pREG_SHL1C0_CFG2;
cfg |= 0x3000;
*pREG_SHL1C0_CFG2 = cfg;
}
void ConfigSMC ()
{
*pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN /* Disable secure write transactions */
| ENUM_SMPU_SECURECTL_WNSDIS /* Enable non-secure writes */
| ENUM_SMPU_SECURECTL_RSECEN /* Disable secure read transactions */
| ENUM_SMPU_SECURECTL_RNSDIS /* Enable non-secure read transactions */
| ENUM_SMPU_SECURECTL_SBEDIS); /* Disable bus error */
SetUncached ();

*pREG_SMC0_B0CTL = 0x00200201; /* Bank 0 Control Register: 0 words, disable abort counter, Low active ARDY, Disable ARDY, AMS0 ORed with AOE, Async SRAM, Enable access */
*pREG_SMC0_B0TIM = 0x05130422; /* Bank 0 Timing Register: RAT = 5 Clk, RHT = 1 Clk, RST = 3 Clk, WAT = 4 Clk, WHT = 2 clk, WST = 2 Clk */
*pREG_SMC0_B0ETIM = 0x00020200; /* Bank 0 Extended Timing Register: PWGS = 2 Clk, IT = 0 CLK, TT = 2 Clk, PREAT = 0, PREST = 0 */



/* configure GPIO ports */
/* unlock everything */
*pREG_PORTA_LOCK = 0;
*pREG_PORTB_LOCK = 0;
*pREG_PORTC_LOCK = 0;
*pREG_PORTD_LOCK = 0;
*pREG_PORTE_LOCK = 0;

/* configure muxes */
*pREG_PORTA_MUX = 0x00000000; // All GPIO
*pREG_PORTB_MUX = 0xFFFFFCFF; // All mux3(SMC) except not connected PB_04
*pREG_PORTC_MUX = 0xC0000003; // All mux0 except mux3(00, 15) and GPIO(12,13)
*pREG_PORTD_MUX = 0xFF00558F; // GPIO(02,08,09,10,11,14), mux1(03,04,05,06,07), mux3(00,01,12,13,15)
*pREG_PORTE_MUX = 0x0FFFFF7F; // all mux3 except mux1(03) and GPIO(14,15)

/* 0 - GPIO, 1 - peripheral */
*pREG_PORTA_FER = 0x0000;
*pREG_PORTB_FER = 0xFFEF;
*pREG_PORTC_FER = 0x8FFF;
*pREG_PORTD_FER = 0xF0FB;
*pREG_PORTE_FER = 0x3FFF;

/* 0 - input, 1 - output */
*pREG_PORTA_DIR = 0x400C; // all inputs except 02, 03, and 14 which are test point outputs
*pREG_PORTB_DIR = 0x0000; // all inputs
*pREG_PORTC_DIR = 0x1000; // all inputs except 12 which is test point output
*pREG_PORTD_DIR = 0x0000; // all inputs
*pREG_PORTE_DIR = 0x0000; // all inputs

}

added the screenshot for timing diagram
[edited by: eletronicRajesh at 9:00 AM (GMT -5) on 23 Nov 2022]