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mismatch in SMC timings for ADSP-SC584 EZ-KIT lite

Category: Software
Product Number: ADSP-SC584
Software Version: Cross Core

Hi fellow Engineers,

I need to interface SRAM based FPGA through SMC interface to the ADSP-SC584 processor. I want to check the cycles taken to complete the read and write from SMC interface 

As per ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Rev 1.0 (HRM) >> page 11-8: >> Static memory Controller (SMC) section, Basic Asynchronous SRAM write followed by read, I programmed the parameters as mentioned in it. 

  • RAT: 5  RHT: 1  RST: 3  WAT: 4  WHT: 2  WST: 2  Turnaround transition time = 2 cycles , Idle transition time = 0 cycles. 
  • based on timing diagram as shown in the HRM it should take for READ9-SCLK_0 cycles and for WRITE:  10 SCLK_0  , where SCLK_0 (100MHZ) = 1/4 CCLK (=400 MHZ) 
  • for cycles.h the required -DDO_CYCLE_COUNTS in compiler flags is added
  • Evaluation board: ADSP-SC584-EZ-KIT-LITE

but the result of cycles taken are not matching with expected cycle counts from cycles.h basic cycle counting method. 

the observed cycles for READ: 130 , Write: 15 

here is the code i've used to get the SMC read and write cycle counts. Please assist in clarifying the correct cycle count and best way to program the SMC interface. 


Cortex -Core 0

#include <sys/platform.h>
#include <sys/adi_core.h>
#include "adi_initialize.h"
#include <stdio.h>

int main()

return 0;


#include <builtins.h>
#include <sys/platform.h>
#include <sys/adi_core.h>
#include <cycle_count.h>
#include <stdio.h>
#include <cycles.h>
#include <time.h> //for CLOCKS_PER_SEC
#include <sysreg.h>
#include <defSC584.h>
#include <platform_include.h>

void SetUncached(void);
void ConfigSMC(void);
#define CLOCKS_PER_SEC 400000000LL

main ()
cycle_t s, a, t, b;
volatile unsigned int foo;

adi_initComponents ();
ConfigSMC (); // setting the CTL, TIM, ETIM registers, uncached SMC memory

START_CYCLE_COUNT(s); // start the counter

foo = *(volatile unsigned int*) (0x40000000); //read from SMC start address

STOP_CYCLE_COUNT(t, s); // stop the counter
PRINT_CYCLES("\nRead = ", t);

return 0 ;

void SetUncached (void)
uint32_t cfg;

*pREG_SHL1C0_RANGE_START6 = 0x40000000; // SMC0 start address
*pREG_SHL1C0_RANGE_END6 = 0x43FFFFFF; // SMC0 End address
cfg = *pREG_SHL1C0_CFG2;
cfg |= 0x3000;
*pREG_SHL1C0_CFG2 = cfg;
void ConfigSMC ()
*pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN /* Disable secure write transactions */
| ENUM_SMPU_SECURECTL_WNSDIS /* Enable non-secure writes */
| ENUM_SMPU_SECURECTL_RSECEN /* Disable secure read transactions */
| ENUM_SMPU_SECURECTL_RNSDIS /* Enable non-secure read transactions */
| ENUM_SMPU_SECURECTL_SBEDIS); /* Disable bus error */
SetUncached ();

*pREG_SMC0_B0CTL = 0x00200201; /* Bank 0 Control Register: 0 words, disable abort counter, Low active ARDY, Disable ARDY, AMS0 ORed with AOE, Async SRAM, Enable access */
*pREG_SMC0_B0TIM = 0x05130422; /* Bank 0 Timing Register: RAT = 5 Clk, RHT = 1 Clk, RST = 3 Clk, WAT = 4 Clk, WHT = 2 clk, WST = 2 Clk */
*pREG_SMC0_B0ETIM = 0x00020200; /* Bank 0 Extended Timing Register: PWGS = 2 Clk, IT = 0 CLK, TT = 2 Clk, PREAT = 0, PREST = 0 */

/* configure GPIO ports */
/* unlock everything */

/* configure muxes */
*pREG_PORTA_MUX = 0x00000000; // All GPIO
*pREG_PORTB_MUX = 0xFFFFFCFF; // All mux3(SMC) except not connected PB_04
*pREG_PORTC_MUX = 0xC0000003; // All mux0 except mux3(00, 15) and GPIO(12,13)
*pREG_PORTD_MUX = 0xFF00558F; // GPIO(02,08,09,10,11,14), mux1(03,04,05,06,07), mux3(00,01,12,13,15)
*pREG_PORTE_MUX = 0x0FFFFF7F; // all mux3 except mux1(03) and GPIO(14,15)

/* 0 - GPIO, 1 - peripheral */
*pREG_PORTA_FER = 0x0000;

/* 0 - input, 1 - output */
*pREG_PORTA_DIR = 0x400C; // all inputs except 02, 03, and 14 which are test point outputs
*pREG_PORTB_DIR = 0x0000; // all inputs
*pREG_PORTC_DIR = 0x1000; // all inputs except 12 which is test point output
*pREG_PORTD_DIR = 0x0000; // all inputs
*pREG_PORTE_DIR = 0x0000; // all inputs


added the screenshot for timing diagram
[edited by: eletronicRajesh at 9:00 AM (GMT -5) on 23 Nov 2022]
  • Hi,

    We are looking this query, we will get back to you as soon as possible.

    Divya P

  • Hi Rajesh,

    We tried to replicate the issue using the code snippet you have shared.

    We would suggest you to use the "asm("sync;");"  instruction after write operation in the SHARC+ and check the result.
    Please find the attached example code where we get the similar cycles for both read and write. Please find the attached screenshot for your

    Please let us know if you need further assistance.


  • Thanks Divya - for quick response. let me try this. 

    looks like the screenshot attachment is missed. please attach it. 

    Regards ! 

  • Hi,

    Please find the screenshots.


  • Hi Divya

    as per datasheet + the configuration done in the C code it should take 

    • READ:  9-SCLK_0 cycles and observed time (in screenshot provided above) = 681 CCLK cycles = ~ 170 SCLK_0 cycles 

    • for WRITE:  10 SCLK_0, where SCLK_0 (100MHZ) = 1/4 CCLK (=400 MHZ) and observed time (in screenshot provided above) = 623 CCLK cycles = ~ 156 SCLK_0 cycles

    could you assist in explaining the huge gap in observed and expected cycles takes for the read and write? 

    Thanks & regards


  • Hi Rajesh,

    In our code, default congratulations of the Core Clock to 450 MHz and the System Clock to 225 MHz is used.  Also cycles taken for SMC read and write for 24 bytes.


  • Hi Divya 

    the query still remains unanswered. 

    for 24 bytes read = 681 cycles => for 8 bytes = 227 cycles (not 9 cycles)

    for 24 bytes write = 623 cycles => for 8 bytes = ~ 208 cycles (not 10 cycles)  

    As the code shared earlier is not demonstrating the claims as per hardware reference manual and not providing any clarity on huge mismatch in SMC read write timings, could you provide any sample code which could demonstrate the cycle count mentioned in hardware reference manual as per the screenshot mentioned above on Nov 23?  

    please assist in this matter asap.


  • Hi team 

    we did not get the read write cycles as mentioned in the HRM using the EZ-Lite with ADSP-SC584 

    however, we made one custom card with ADSP-21583 processor  and there the SMC interface  is connected to SRAM of the FPGA. and we were able to get the read-write cycles as per HRM. 

    in SMC.CTL register we have option to choose AMS / AMS OR AOE/ AMS OR ARE/ AMS OR AWE ... this is creating set up and hold time mismatch as given in datasheet. so we used AMS only as default and did our calculations. 

    if possible please look at validating the SMC interface and the set up and hold time as mentioned in datasheet. 



  • Hi Rajesh,

    To assist you better, can you please share more details about expected and observed timing details when changing the value in SMC_B0CTL.SELCTRL


  • hi Divya 

    as per the datasheet, we are expected to observe these timings. 


    1. for read, SMC_B0CTL.SELCTRL = 1 (= AMS OR ARE ) as well as 2 (=AMS OR AOE) allows to read from SMC... but the AMS and ARE signals are asserted at same clock edge and the tAMSARE , tHARE are not observed
    2. for read and write the AMS only option itself asserts ARE and AWE signals and hence the assertion of read write signals after any required setup delay of AMS assertion is not observed. 

    for time being, we are using AMS only option and considering it resolved. but clarity of signals provided is missing in HRM and datasheet.