Synchronizing data from AD73360 on SC573

Hi greeny

Can you please share how you have the two devices connected?

Are you performing a Frame Sync Loopback?

How is the SRU configured?

Thanks.

Chris

Hi Chris,

Our setup is most similar to Figure 13 of the AD73360 manual. With two ADCs we've connected SDOFS of ADC1 to SDIFS of ADC2. SDIFS of ADC1 to SDOFS of ADC2 are connected together and this is the FS Input/output connected to the SC573.

The code for our SRU setup is below. We're configured for an externally provided frame sync (ADCs provide it) and this is supplied to both SPORT interfaces we're using - the TX and RX interfaces.

void SRUInit()
{
    // DAI0_PB02 provides clock for SPORTA & SPORTB (externally supplied CLK)
    SRU(LOW, DAI0_PBEN02_I);
    SRU(LOW, DAI0_PB02_I);
    SRU(DAI0_PB02_O, SPT0_ACLK_I);
    SRU(DAI0_PB02_O, SPT0_BCLK_I);

    // DAI0_PB04 provides frame sync for SPORTA & SPORTB (externally supplied FS)
    SRU(LOW, DAI0_PBEN04_I);
    SRU(LOW, DAI0_PB04_I);
    SRU(DAI0_PB04_O, SPT0_AFS_I);
    SRU(DAI0_PB04_O, SPT0_BFS_I);

    // SPORTA outputs data to DAI0_PB01
    SRU(HIGH, DAI0_PBEN01_I);
    SRU(SPT0_AD0_O, DAI0_PB01_I);

    // DAI0_PB03 is a data input to SPORTB
    SRU(LOW, DAI0_PBEN03_I);
    SRU(LOW, DAI0_PB03_I);
    SRU(DAI0_PB03_O, SPT0_BD0_I);
}

If you use figure 17 as an example 

se is used to index the start of adc samples 

data is out put device 2 adc 1 then device 1 adc 1 then frame sync sdofs 

if you keep clocking you will get the next 2 adc samples device 2 adc 2 then device 1 adc 2 then frame sync sdofs. 

Using SE as the start of adc samples and frame sync to increment which adcs have been transferred you should be able to store them correctly so you understand which adc is in which memory location. 

se high from dsp 

32 clocks device2 adc 1 device1 adc 1  SDOFS  frame sync from AD73360

32 clocks device2 adc 2 device1 adc 2  SDOFS  frame sync

32 clocks device2 adc 3 device1 adc 3  SDOFS  frame sync

32 clocks device2 adc 4 device1 adc 4  SDOFS  frame sync

32 clocks device2 adc 5 device1 adc 5  SDOFS  frame sync

32 clocks device2 adc 6 device1 adc 6  SDOFS  frame sync

se low from dsp

you will need to define how many devices are in the chain

This is all on page 23 https://www.analog.com/media/en/technical-documentation/data-sheets/ad73360.pdf

sc573 is not my part so really can't help with that one. 

Dave

Thanks Dave,

We think that we can do what you describe, our issue is because there is a delay from when we set SE and when we have our DMA enabled. This would require some refactoring on our part but is definitely doable.

We did get our samples aligned but aren't sure if it is just luck. Our current solution is to assert SE, configure the ADC, and then de-assert SE. Later when the thread that receives and processes samples is up and running we again assert SE. When we do this, our samples are aligned.

A new question is - does the ADC always output the first channels data after SE is asserted?

-Shawn

Yes that is my understanding some of the timing diagrams show this and maybe the pin description indicates this for the SE pin.

there also may be a frame sync between daisy chain adc values. I think I read teh diagram wrong.

32 clocks device2 adc 1 SDOFS   device1 adc 1  SDOFS  frame sync from AD73360

Dave

How confident are you that the ADC will send the first channel of data after we toggle the SE pin in this way? The timing diagrams certainly suggest this and the description of the SE pin says that it resets internal counters. This needs to work every time!

-Shawn

I can only go by the datasheet I think it works this way but I don't have a way to test it. 

Dave

Hi,

For ADSP-SC573-SHARC the TDM multiplexed data get sampled with a single frame sync. So basically as soon as frame sync signal is asserted all the multiplexed data across all the channels will get through continuously.

Regards,
Anand Selvaraj.

Hi Dave,

Digging this one back up... what we had implemented is using the SE pin in an effort to control when the ADC starts sampling and align the SHARC SPORT RX DMA with the output from the ADC. This appeared to work well but seems to be subject to some timing problems. We didn't try the toggling of the SE pin as I believe timing is too tight to do this and the FAQ for the AD73360 advises against it: Change sample rate by controlling SE pin. - Documents - Audio - EngineerZone (analog.com)

There's two issues then - the first is getting SHARC aligned with the ADC, this seems to be a matter of getting timing right. The second is how to detect a misalignment - which can be caused by ESD. In one case we're using cascaded AD73360 parts and have unused channels, these channels can be tied to ground, vcc, or the reference voltage and monitored to see where they are in the stream. However in another product only one AD73360 is used and there are no free channels. How can we detect when the first sample comes from the ADC... possibly a hardware timer on the SHARC?

Looking for any more suggestions here!

Cheers

Hi Anand,

There is not a single frame sync from the AD73360. See the below figure from the AD73360 manual. SDOFS is asserted for every channel of data and there is no indicator when the first channel of data is sent. It's some time after SE is asserted. If the timing is not right in the SHARC and it begins receiving after the first sample the only other method is to some how detect where the gap is between sample sets - in our case this gap is 4 microseconds. SHARC TDM does not appear to support this condition.

We've gotten some more captures from our scope and can see that toggling the SE pin is working as we want it to. When the pin is de-asserted the ADC stops transferring data, when it is asserted again ADC starts sending samples from the first channel.

Our problem is with debug vs release builds :). Specifically with the definition `ADI_DEBUG`, when this is enabled SE toggling is working fine. When disabled, the SE pin is not toggled at all. We will track this down on our end - could be the optimizer removing code that we'd rather it not.

Hi Shawn,

Debug and Release are simply names for different configurations of your project, allowing you to individually set Compiler, Linker, Loader, etc, options differently based on your requirements.

The defaults of Debug and Release differ in that Debug generates Debug information and does not perform optimization, while the Release version does not generate debug information but does enable optimization.

Note that the default setting (or "debug" mode within the IDE) is for non-optimized compilation in order to assist programmers in diagnosing problems with their initial coding. The optimizer is enabled through the IDE by selecting Project > Properties >C/C++ Build > Settings > Tool Settings > Compiler > General > Enable optimization, or by using the -O switch (-O[0|1] ). A "release" build from within the IDE automatically enables optimization.

Regards,
Divya.P

Hi Shawn,

Debug and Release are simply names for different configurations of your project, allowing you to individually set Compiler, Linker, Loader, etc, options differently based on your requirements.

The defaults of Debug and Release differ in that Debug generates Debug information and does not perform optimization, while the Release version does not generate debug information but does enable optimization.

Note that the default setting (or "debug" mode within the IDE) is for non-optimized compilation in order to assist programmers in diagnosing problems with their initial coding. The optimizer is enabled through the IDE by selecting Project > Properties >C/C++ Build > Settings > Tool Settings > Compiler > General > Enable optimization, or by using the -O switch (-O[0|1] ). A "release" build from within the IDE automatically enables optimization.

Regards,
Divya.P