Synchronizing data from AD73360 on SC573

Hi greeny

Can you please share how you have the two devices connected?

Are you performing a Frame Sync Loopback?

How is the SRU configured?

Thanks.

Chris

Hi Chris,

Our setup is most similar to Figure 13 of the AD73360 manual. With two ADCs we've connected SDOFS of ADC1 to SDIFS of ADC2. SDIFS of ADC1 to SDOFS of ADC2 are connected together and this is the FS Input/output connected to the SC573.

The code for our SRU setup is below. We're configured for an externally provided frame sync (ADCs provide it) and this is supplied to both SPORT interfaces we're using - the TX and RX interfaces.

void SRUInit()
{
    // DAI0_PB02 provides clock for SPORTA & SPORTB (externally supplied CLK)
    SRU(LOW, DAI0_PBEN02_I);
    SRU(LOW, DAI0_PB02_I);
    SRU(DAI0_PB02_O, SPT0_ACLK_I);
    SRU(DAI0_PB02_O, SPT0_BCLK_I);

    // DAI0_PB04 provides frame sync for SPORTA & SPORTB (externally supplied FS)
    SRU(LOW, DAI0_PBEN04_I);
    SRU(LOW, DAI0_PB04_I);
    SRU(DAI0_PB04_O, SPT0_AFS_I);
    SRU(DAI0_PB04_O, SPT0_BFS_I);

    // SPORTA outputs data to DAI0_PB01
    SRU(HIGH, DAI0_PBEN01_I);
    SRU(SPT0_AD0_O, DAI0_PB01_I);

    // DAI0_PB03 is a data input to SPORTB
    SRU(LOW, DAI0_PBEN03_I);
    SRU(LOW, DAI0_PB03_I);
    SRU(DAI0_PB03_O, SPT0_BD0_I);
}

Hi Greeny,
 
We have an example for SPORT using TDM mode. Please download “ADSP-SC5XX Board Support Package - Current Release (Rev. 2.0.2)” from the below link:
download.analog.com/.../ADI_ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2.exe

After installation, Examples available in the below path:
<installation path>\ADSP-SC5xx_EZ-KIT_Lite-Rel2.0.2\ADSP-SC5xx_EZ-KIT\Examples\drivers\adc\adau1979

The mode of operation of this example (Playback or Analog Loopback) can be configure in adc_dac_playback.h header file. The #define PLAYBACK is defined by default and builds the example for playback mode. If this #define is commented out the example builds for analog loopback mode. For playback mode there is an additional #define TDM_MODE that determines whether the playback operates in I2S (stereo mode) or multichannel (TDM mode). For more details, please refer the readme file available in the example.

Please let us know if you need any further assistance.

Regards,
Anand Selvaraj.
 

Thanks, I will have a look at this example. I had a go at turning on TDM mode but need to be more thorough.

My understanding of the SHARC's TDM is that it expects a single frame sync and then 'n' channels of data. In contrast, the ADC outputs a frame sync per-channel. How would turning on TDM in the SHARC solve this problem? Is my understanding incorrect here?

-Shawn

Is my understanding correct that the SHARC TDM expectations are different from what the ADC provides?

If you use figure 17 as an example 

se is used to index the start of adc samples 

data is out put device 2 adc 1 then device 1 adc 1 then frame sync sdofs 

if you keep clocking you will get the next 2 adc samples device 2 adc 2 then device 1 adc 2 then frame sync sdofs. 

Using SE as the start of adc samples and frame sync to increment which adcs have been transferred you should be able to store them correctly so you understand which adc is in which memory location. 

se high from dsp 

32 clocks device2 adc 1 device1 adc 1  SDOFS  frame sync from AD73360

32 clocks device2 adc 2 device1 adc 2  SDOFS  frame sync

32 clocks device2 adc 3 device1 adc 3  SDOFS  frame sync

32 clocks device2 adc 4 device1 adc 4  SDOFS  frame sync

32 clocks device2 adc 5 device1 adc 5  SDOFS  frame sync

32 clocks device2 adc 6 device1 adc 6  SDOFS  frame sync

se low from dsp

you will need to define how many devices are in the chain

This is all on page 23 https://www.analog.com/media/en/technical-documentation/data-sheets/ad73360.pdf

sc573 is not my part so really can't help with that one. 

Dave

Thanks Dave,

We think that we can do what you describe, our issue is because there is a delay from when we set SE and when we have our DMA enabled. This would require some refactoring on our part but is definitely doable.

We did get our samples aligned but aren't sure if it is just luck. Our current solution is to assert SE, configure the ADC, and then de-assert SE. Later when the thread that receives and processes samples is up and running we again assert SE. When we do this, our samples are aligned.

A new question is - does the ADC always output the first channels data after SE is asserted?

-Shawn

Yes that is my understanding some of the timing diagrams show this and maybe the pin description indicates this for the SE pin.

there also may be a frame sync between daisy chain adc values. I think I read teh diagram wrong.

32 clocks device2 adc 1 SDOFS   device1 adc 1  SDOFS  frame sync from AD73360

Dave

How confident are you that the ADC will send the first channel of data after we toggle the SE pin in this way? The timing diagrams certainly suggest this and the description of the SE pin says that it resets internal counters. This needs to work every time!

-Shawn

I can only go by the datasheet I think it works this way but I don't have a way to test it. 

Dave