I have two SPORTs sending data directly to each other through DMA interrupting on XCount expiry that used to be configured through the ADI driver and my setup worked without issue. Prior to my recent changes the DMA channels were configured to do queued 1D transfers (adi_sport_SubmitBuffer) to simulate ping-pong buffering. This was changed to configure the SPORTs and DMA channels directly through their respective registers for more flexibility in an attempt to perform 2D register-autobuffer transfers. The receive end's DMA ping-pong buffer still gets populated without distortion although I am now having issues with the data once it has been copied from the ping-pong buffer.
During the Rx DMA's interrupt service routine the ping-pong buffer's data is separated by Left and Right channels which are each copied into a separate 64-sample buffer and then scaled to range from -1.0 to +1.0. The resulting data is now repeated and appears to be broken up partway through a buffer copy. The first photo below shows a zoom-in on a single 64-sample buffer while the second photo below shows a 2048-sample window or the resulting data.
What I am expecting from a single-channel buffer is what I used to observe shown below. Once again, the first photo shows a single 64-sample buffer while the second photo shows a 2048-sample window.
For context, my SPORT and DMA registers are currently configured as follows:
Rx
DMA_CFG: 0x05501523
DMA_XCNT: 0x00000010
DMA_XMOD: 0x00000020
DMA_YCNT: 0x00000002
DMA_YMOD: 0x00000020
SPORT_CTL: 0x00019973
Tx
DMA_CFG: 0x05501521
DMA_XCNT: 0x00000010
DMA_XMOD: 0x00000020
DMA_YCNT: 0x00000002
DMA_YMOD: 0x00000020
SPORT_CTL: 0x00019973
In addition, the DMA interrupt service routines now check the appropriate SPORT_ERROR and DMA_STATUS registers for errors, of which none are occurring. They also perform a write-one-to-clear (W1C) operation on the corresponding DMA_STATUS register once the ping-pong data copying is finished. Interestingly, removing this W1C results in the Rx side no longer interrupting after the first time while the Tx side continues to interrupt. Perhaps the DMA interrupt service routines are being run more often than they should be?
What other diagnostic or control measures would be appropriate to take here to find the root of my newfound data corruption? I gave 2D data buffering a try in descriptor-list mode with the same results as described above.