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SC589 Register-Autobuffer DMA interrupts do not allow for smooth data copying from a ping-pong buffer

Category: Software
Software Version: CrossCore Embedded Studio 2.8.2

I have two SPORTs sending data directly to each other through DMA interrupting on XCount expiry that used to be configured through the ADI driver and my setup worked without issue. Prior to my recent changes the DMA channels were configured to do queued 1D transfers (adi_sport_SubmitBuffer) to simulate ping-pong buffering. This was changed to configure the SPORTs and DMA channels directly through their respective registers for more flexibility in an attempt to perform 2D register-autobuffer transfers. The receive end's DMA ping-pong buffer still gets populated without distortion although I am now having issues with the data once it has been copied from the ping-pong buffer.

During the Rx DMA's interrupt service routine the ping-pong buffer's data is separated by Left and Right channels which are each copied into a separate 64-sample buffer and then scaled to range from -1.0 to +1.0. The resulting data is now repeated and appears to be broken up partway through a buffer copy. The first photo below shows a zoom-in on a single 64-sample buffer while the second photo below shows a 2048-sample window or the resulting data.

What I am expecting from a single-channel buffer is what I used to observe shown below. Once again, the first photo shows a single 64-sample buffer while the second photo shows a 2048-sample window.

For context, my SPORT and DMA registers are currently configured as follows:

Rx

DMA_CFG:    0x05501523

DMA_XCNT:  0x00000010

DMA_XMOD: 0x00000020

DMA_YCNT:  0x00000002

DMA_YMOD: 0x00000020

SPORT_CTL: 0x00019973

Tx

DMA_CFG:    0x05501521

DMA_XCNT:  0x00000010

DMA_XMOD: 0x00000020

DMA_YCNT:  0x00000002

DMA_YMOD: 0x00000020

SPORT_CTL: 0x00019973

In addition, the DMA interrupt service routines now check the appropriate SPORT_ERROR and DMA_STATUS registers for errors, of which none are occurring. They also perform a write-one-to-clear (W1C) operation on the corresponding DMA_STATUS register once the ping-pong data copying is finished. Interestingly, removing this W1C results in the Rx side no longer interrupting after the first time while the Tx side continues to interrupt. Perhaps the DMA interrupt service routines are being run more often than they should be?

What other diagnostic or control measures would be appropriate to take here to find the root of my newfound data corruption? I gave 2D data buffering a try in descriptor-list mode with the same results as described above.

  • Hi,

    Can you please provide more information on below points to assist you better on this.

    1. Which SPORT mode are you using?

    2. Did you enable the SPU_SECUREP register for DMA channel?

    3. Did you properly configure the SPORT Configuration like as( Framesync,Clock,Data for Tx and Rx side)?

    4. In one Dimensional DMA Autobuffer, it's runs successfully?Did you get the proper 64-Sample buffer and 2048-sample window? Are you expecting sine wave?

    5.Regarding "The ping-pong buffer's data is separated by Left and Right channels which are each copied into a separate 64-sample buffer" >>>Could you please explain in details to assist you better on this.

    Regards,
    Divya.P

  • Hello,

    Below are answers to the questions you have posed:

    1. Both SPORTs are running in I2S Mode (DSP-I2S)

    2. Yes, the SPU has been correctly configured by adi_spu_EnableMasterSecure calls using the SPORT0A/B DMA peripheral numbers outlined in the hardware reference manual. This is corroborated by these DMA engines working when performing sequential 1D stop-flow DMA transfers.

    3. Yes, the SPORT configuration register contents shown above allow for the data to be successfully sent and interpreted as expected when performing 1D stop-flow DMA transfers to/from the SPORTs. The SPORTs' configurations have not been changed when attempting to switch over to 2D autobuffer-flow DMA transfers.

    4. Not quite, it runs successfully when queueing 1D stop-flow DMA transfers using adi_sport_SubmitBuffer. While doing this, I got the 2048-sample and 64-sample output buffer contents that I expected. I am expecting a clean sine wave ranging from -1.0 to +1.0.

    5. This statement refers to how the data received from the Rx SPORT is processed upon arrival in its target DMA ping-pong buffer. The data being sent across the SPORTs are interleaved such that all even-numbered samples comprise a Left channel while all odd-numbered samples comprise a Right channel. When a 128-sample DMA transfer is finished (XCnt Expiry), the resulting interrupt service routine copies the Left and Right channel data into their own 64-sample buffer.

    I hope this helps provide context to the issue I am having.

    Thank you for your attention.

  • Hi,


    Can you please share your simple project which simulates this issue. If you're unable to share your project on this forum, you can send project to Processor Support through: processor.support@analog.com.
    Please make sure to add the link of this EZone thread while contacting private support.

    Thanks,
    Anand Selvaraj.