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How many DAI pins can be connected by PCG_CLKA_O/PCG_FSA_O

Category: Hardware
Product Number: ADSP-21571

When i was using PCG clock as input to sport and peripherals ,  at first time , i connect 8 pins with PCG_CLKA_O , there will be no signal output from sport after serveral minutes running,and recover immediatly .  But if i connect PCG_CLKA_O with only 4 pins ,and other pins routed by other DAI pin , it will be no this problem .  so i suspect that it is beyond the drive capacity of PCG_CLKA_O in the case of connectting with 8 pins .  

so my questions is how many pins PCG_CLKA_O or DAI PINS can be connected at same time, if used as output .And is there any document about that ?

thanks.

  • Hi,

    Please provide your comments on below questions to narrow down the issues
    1. What are the peripherals are connected with PCG_CLKA_O in ADSP-21571? Like SPORT 0, SPORT 1, SPDIF etc
    2. Also, share us the simple block diagram of connection between PCG_CLKA_O to ADSP-21571?

    Regards,
    Divya.P

  • Hi,

    I met this problem too. I also suspect the driver capacity of DAI pins and PCG source.

    I don't think it's due to what sport I use. I have this problem in many sports, and it's easily occured when I drive several sports using one group of clk ana fs.

    What interest me is that if I use PCG source send to DAI pins to drive several sports, it's ealisy to report HW fs error. However it can be improved when I use PCG directly drive the sports.

  • thanks your reply ,

    here is my code

        SRU(PCG0_CLKA_O, SPT0_ACLK_I);
        SRU(PCG0_CLKA_O, SRC0_CLK_OP_I);
        SRU(PCG0_CLKA_O, SRC1_CLK_OP_I);
        SRU(PCG0_CLKA_O, SRC2_CLK_OP_I);
        SRU(PCG0_CLKA_O, SRC3_CLK_OP_I);


        SRU(PCG0_FSA_O, SPT0_AFS_I);
        SRU(PCG0_FSA_O,SRC0_FS_OP_I);
        SRU(PCG0_FSA_O,SRC1_FS_OP_I);
        SRU(PCG0_FSA_O,SRC2_FS_OP_I);
        SRU(PCG0_FSA_O,SRC3_FS_OP_I);
       
            SRU(PCG0_FSA_O, SPT2_AFS_I);
            SRU(PCG0_CLKA_O, SPT2_ACLK_I);

            SRU(PCG0_FSA_O, SPT3_BFS_I);
            SRU(PCG0_CLKA_O, SPT3_BCLK_I);
           
            SRU(PCG0_FSA_O, SPT3_AFS_I);
            SRU(PCG0_CLKA_O, SPT3_ACLK_I);

            SRU(PCG0_FSA_O, SPT1_AFS_I);
            SRU(PCG0_CLKA_O, SPT1_ACLK_I);

            SRU(PCG0_FSA_O, DAI0_PB02_I);
            SRU(PCG0_CLKA_O, DAI0_PB01_I);
            SRU(PCG0_FSA_O, DAI0_PB18_I);
            SRU(PCG0_CLKA_O, DAI0_PB17_I);
     
  • agree with you , but never saw offical document about it.

  • Hi,

    The DAI pins has some driving limitations. We can't able to connect more load.

    Thanks,
    Anand Selvaraj.

  • Hi,

    If I drive several ports using a single DAI pin, as you said the DAI pin can't offer enough driver capacity. So I would like to add a driver chip outside to strengthen the driver capacity. The DAI output connect to the driver chip input and the driver chip output connect to the several receiver ports. Could you please recommend which driver chip can I use in this situation?

    Thanks.

  • Hi Foster,

    We don’t have any recommended chip for this. There are lot of clock buffers available. You can select one for your design.

    Thanks,
    Anand Selvaraj.