There doesn't seem to be any hardware reference design for the ADSP-2156x SHARCS with the 120-Lead LQFP package.
Specifically, for power supply bypassing.
In the schematics for the 21569 EZ-Kit etc. the bypassing scheme is best described as.... random. There are lots of caps of lots of different values, in various ratios to each other.
Looking for something straight forward to follow... typically something like, 100n cap per VDD_xxx pin with some bulk caps per VDD_xxx.
Also things like whether 10n is only necessary for 800/1000MHz.
Some kind of reference would be nice.
Added additional details
[edited by: InoJosh at 11:29 PM (GMT -4) on 26 May 2022]