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ADSP-21573 SPI slave/master boot, PC00 / nSPI2_RDY

Hi All,

we have designed custom boards for the ADSP-21573 in two versions:
- one booting DSP in SPI master mode from flash
- one booting DSP in SPI slave mode from another processor

(1.) Is 10k the recommended value for the pull up resistor for PC00 / nSPI2_RDY (as seen in the HWR p.45-29) ?

(2.) How is the pin PC00 involved in booting in SPI master mode from flash ?
We experience the need to pull it up to VCC to make the DSP start reading from flash after Reset / Power Up.

Thanks in advance,
David

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  • Hi,

    The SPI_RDY signal is an optional flow signal. It is an output in slave mode, input in master mode.

    In SPI slave boot mode, SPIx_RDY functionality is critical. The SPIx_RDY output is used for back pressure and requires a pulling resistor. The boot code requires the SPIx_RDY signal function as active-low. The host is only permitted to transfer data when SPIx_RDY is in the active state. This functionality allows the processor to hold off the host while the processor is in reset or executing the pre-boot and processor initialization sequences. The SPI is configured to deassert SPIx_RDY when the receive FIFO is filled to 75% or more.

    Regards,
    Anand Selvaraj.

  • Hi Anand,

    thanks for your reply.

    1.)
    Can you please give an advice for the size of the pull up resistor to be used in custom PCB designs to pull SPIx_RDY up to VCC ?

    2.)
    If SPIx_RDY is an input in master mode, has it any functional impact for master boot mode ? E.g. will it be evaluated as a back pressure channel this way around as well but then maybe driven by a flash ?

    Thanks & Regards,

    David

  • Hi,

    Regarding, “Can you please give an advice for the size of the pull up resistor to be used in custom PCB designs to pull SPIx_RDY up to VCC?”
    >> You can use 10K pullup resistor for your design.

    Regarding, “If SPIx_RDY is an input in master mode, has it any functional impact for master boot mode ? E.g. will it be evaluated as a back pressure channel this way around as well but then maybe driven by a flash ?
    >> The flow control features enable slow slave devices to interface with fast master devices by providing an SPI ready pin (SPI_RDY) which flexibly controls the transfers.
     
    Regards,
    Anand Selvaraj.
     

  • Hi Anand,

    thanks for your reply.

    Please be more precise regarding my second question: does the DSP rely on this signal if booting in SPI master boot mode from external flash or will this input signal be ignored by DSP ?

    Thanks & Regards,
    David

  • Hi,

    The SPI Master boot mode doesn’t need for SPI_RDY signal . It is mainly used for SPI slave boot mode.
    Does your flash device has SPI_RDY signal?
     
    Regards,
    Anand Selvaraj.
     

  • Hi Anand,

    thanks for the information.

    No, our flash has no such READY signal.
    But while SPI master boot tests we experienced issues keeping the SPI_RDY signal pulled up via 10k resistor.
    With your verification that this signal is not needed for SPI master boot mode we will forward those findings to the hardware engineering for PCB review.

    Thanks & Kind Regards,
    David

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  • Hi Anand,

    thanks for the information.

    No, our flash has no such READY signal.
    But while SPI master boot tests we experienced issues keeping the SPI_RDY signal pulled up via 10k resistor.
    With your verification that this signal is not needed for SPI master boot mode we will forward those findings to the hardware engineering for PCB review.

    Thanks & Kind Regards,
    David

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