locking cache with program memory from DDR external memory

Hi, 

I am interested in learning how to lock L1 cache with program memory read from the DDR external memory with a SC589 target.
There is an example for Sharc+ about locking the chache memory after writing some data into it but I am not sure how to do it with program memory (functions or libraries) mapped to the external memory. 

Some documentation mentions to perform  dummy reads in the functions you are interested in, and then to lock the cache. How it behaves with nested functions?Does it brings to L1 all the related instructions?in the example all sub-functions if mapped in external memory?
example: 

void func (int i)
{
    switch (i):
   {
      case 0: subfunction1():
      case 0: subfunction2():
      case 0: subfunction3():
      case 0: subfunction4():
    }
}

 
How to be sure they are executed afterwards from cache memory?is it possible to keep track of it? 

Mainly to have an optimized and deterministic way of calling functions in real time. 

Regards and thanks in advance!

BB



example added
[edited by: BlackBeauty at 3:39 PM (GMT -5) on 21 Jan 2021]
  • 0
    •  Analog Employees 
    on Feb 26, 2021 4:26 PM

    Hi,

    The data cache attached to L1 block 1 caches all the external memory access requests coming over the DM bus (DM cache). Similarly, the data cache attached to L1 block 2 caches all external memory data access  requests coming over the PM bus (PM cache).To begin with, I would suggest you to take a look at the application note EE-400(Using Cache on ADSP-SC5xx/ADSP-215xx SHARC+® Processors). The EE note can be downloaded from the below link.
    www.analog.com/.../EE-400.pdf

    There are few example codes associated with this EE note. The example code can be downloaded from the below link.
    www.analog.com/.../EE-400.zip

    Regards,
    Anand Selvaraj.