Using just 1 SPORT, SPORT0B, as RX with DMA1. Interrupt handler is installed, SCP stuff is setup (SPORT0B and SPORT0B DDE).
Things works when running a debug session only when a breakpoint is set at this line:
*pREG_DMA1_CFG |= BITM_DMA_CFG_EN; // Breakpoint here
*pREG_SPORT0_CTL_B |= BITM_SPORT_CTL_B_SPENPRI;
If a breakpoint is not set, then as soon as SPORT0B is enabled, I get a DMA error, ERRC = 3 (Memory Access or Fabric Error).
Again: as long as there is a breakpoint at that line, as soon as it stops on that breakpoint and immediately hit Resume, everything runs without issue. If I run from the start of the debug session without the breakpoint, the error occurs.
I tried putting some delay before the instruction that needs to stop on the breakpoint, and that didn't make a difference. I tried re-ordering things to see if it made any difference, but nothing helped.
I am really at a loss as to what is going on here. Any ideas? Thanks!
Hi,1) Is the SPU secure registers enabled for SPORT DMA channels? Please refer Table 30-11 in ADSP-2156x Hrm at below.www.analog.com/.../adsp-2156x_hwr.pdf2) Can you share the code snippet for SPORT configuration?3) Is the SPORT is communicating with another half sport/sport or with codec?4) What is the source of SPORT clock and FS?Regards,Anand Selvaraj.
1) Yes, the SPU registers are configured. Without that, my understanding is it would not work at all, whereas it does work right now as long as a breakpoint is set on the line that enables the DMA.
2) It isn't so much a snippet as a whole lot of code (I adapted bm_audio_flow driver from the SHARC Audio Module). I think I would have to send the project.
3) SPORT BCLK and FS as sourced externally from DAI pins (coming from another chip).
I have 2 SHARCS that are doing this now. At first I was only working on one of them, but have begun work on the second. The second receives TDM data from the first, and it also must have a breakpoint set on the DMA enable line in order to prevent the DMA error from occuring.
Hi,Can you try with adding SHARC offset address to DMA start address of transmit and receive channels?Please refer the attached code and screen shots.
The buffers are in L2 SRAM ("seg_l2_dmda_bw").
And it does work, just only works with the breakpoint set.
I still can't get this to work without the breakpoint, and I've run out of things to try...