SC589 Multichannel transmit SPORT DMA does not align with Frame Sync clock


I have a application where multichannel Sport receive data from ADC and sent to DAC via multichannel Sport transmit.

External BCLK and FS are used. 32 Sport channels are used.

Receive Sport is aligned with FS but Transmit Sport does not wait FS signal to arrive. DMA_XCNT_CUR reduce to 13 instead of 32 even clocks are not provided on transmit mode. I could not understand this.

The configuration for receive and transmit mode.

Configure DMA RX and TX 

Configure Multichannel Sport

Enable DMA RX and TX

Enable SPORT RX and TX

Enable BCLK and FS

I enable BCLK and FS as last step to Synchronize the RX and TX on FS at startup. 

Even when clocked are not provided, Transmit DMA count reduce to 13 instead of 32. I do not understand this. 

Thanks for your help in advance.



  • 0
    •  Analog Employees 
    on Jul 24, 2020 2:13 PM 7 months ago


    1) Can you conform how many Sport's are used? Are you reading 32 channel data from codec using TDM format?
    2) Are you using data independent frame sync?
    3) If a SPORT is configured for external frame syncs (SPORT_CTL_A.IFS = 0), then SPORT_AFS is an input signal and the SPORT_DIV_A.FSDIV field of the SPORT_DIV_A register is irrelevant and ignored. By default,
        this external signal is level-sensitive, but it can be configured as an edge-sensitive signal by setting the SPORT_CTL_A.FSED bit. The frame sync is expected to be synchronous with the serial clock. If not, it must
        meet the timing requirements that appear in the Sc58x datasheet.
        NOTE:  SPORT_CTL_A.FSED is valid only in external frame sync mode. In internal frame sync mode, the setting of this bit is irrelevant and ignored.
    4) By default, the frame sync signal is configured to be early ( SPORT_CTL_A.LAFS = 0). The first bit of the transmit data word will be driven one serial clock cycle after the frame sync is asserted (whether sensed externally or internally
        provided), and the first bit of the receive data word is expected to lag the frame sync by one serial clock cycle. The frame sync is not checked again until the entire word has been transferred.
    5) can you share the SPORT and DMA configuration?

    Anand Selvaraj.

  • Hi,

    The issue is solved. The DMA FIFO size is 16 words(32-bit) which is not documented.

    On multichannel SPORT transmit, DMA does not wait for FS detect and fills the DMA FIFO as soon as DMA is enabled. This causes TX SPORT to be misaligned with RX SPORT on which interrupt is generated. The Solution is to set SYNC bit on transmitted DMA that  controls the handling of DMA FIFO between current and next work unit. It means DMA buffers are not switched until last word is sent to the TX SPORT. 

  • Hi MZC,

    could you share more information on the haindling of the SYNC bit? Or do you have a reference or code snippet, where it becomes clearer? 

    Thanks in advance and best regards!

  • 0
    •  Analog Employees 
    on Oct 9, 2020 2:32 PM 4 months ago in reply to Blofeld


    When the transfer direction is memory read/transmit(DMA_CFG.WNR =0) the DMA waits until all data transmits to a peripheral before moving on to the next work unit, clearing the FIFO and pointers.

    When the transfer direction is memory write/receive(DMA_CFG.WNR =1) the DMA ignores the DMA_CFG.SYNC bit value after processing the first work unit of a work unit chain. As a channel can receive data when turned on but idle data from the peripheral can still be in the FIFO even though the channel was not programmed. When the DMA_CFG.SYNC bit field is set at the beginning of a work unit chain (during the first work unit), the DMA clears the FIFO erasing the data put into the FIFO while the channel was idle.

    Please refer Chapter-38 from SC58x HRM at below download link.

    Anand Selvaraj.