ADSP-SC584 memory allocation for ARM to access L1 and L2


I'm trying to allocate the L1 or L2 memory for ARM-Cortex5.

For some reason all the variables are sitting by default in L3 (DDR memory).

Sharc Core has access to all memories.

Can somebody help me to access L1 and L2 in ARM?


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[edited by: lallison at 4:11 PM (GMT 0) on 24 Feb 2020]
  • 0
    •  Analog Employees 
    on Feb 19, 2021 9:05 AM


    By default the ARM default linker definition scripts for ADSP-SC5xx processors place the users' code and data in to L3 memory. L3 is chosen for placement because the amount of L2 memory available to the ARM core is limited.

    The following example will declare an array of 100 integers and place the array in the section .l2_uncached_data.
    int my_array[100] __attribute__ ((section (".l2_uncached_data")));

    The following example will declare a function my_func and place the function into the section .l2_cached_code.
    void __attribute__ ((section(".l2_cached_code"))) my_func(void) {  ...


    For more information, please refer below CCES help:
    CrossCore® Embedded Studio 2.9.1 > ARM® Development Tools Documentation > Cortex-A > Analog Devices ARM Toolchain Manual > Analog Devices Specific Linker Support

    Anand Selvaraj.