I want to make a range of DDR address uncacheable, Please suggest how can i do that?
I am using ADSP-SC589 and CCES 2.8.1.
Moving to ADSP-SC5xx/ADSP-215xx
Please find attached a very basic project which shows that the ARM and SHARC can both read and write shared L3 memory. The example follows the advice, “adding a modified abstract page table to the ARM project and does not raise any exception when written to”. Though the example project is for ADSP-SC584, still you could refer this and modify as per your requirement. A few notes on the example:- This is a very naive example. We don't recommend using hard-coded addresses to share data, as is done for clarity here.- The apt file in the ARM project is modified at line 195- The cache is turned off for the shared L3 memory on the SHARC core, using the adi_cache_set_range API- The example, when run, should print that the value at the L3 address is 1 on the SHARC core, then subsequently 2 on the ARM core. To see this, when creating your Debug Configuration, make sure you remove the Automatic Breakpoint at "main" on Core 1 (SHARC), so that the SHARC core runs without stopping when enabled from the ARM.
Hi,Attached wrong code. Apologies for inconvenience caused. I am attaching the correct project here.Regards,Lalitha.S