We have MCPCM Talk through code current implementation two ADP1939 audio codec's MCLK pin is configured using RX_HDMI clock.
By using this we are able get audio o/p in both Audio codec's.
AD1939A_MCLK_T <= ADV7625_AP1_OUT_MCLK_T; -- route MCLK output from RX_HDMI to AD1939A
AD1939B_MCLK_T <= ADV7625_AP1_OUT_MCLK_T; -- route MCLK output from RX_HDMI to AD1939B
But if we configure one AD1939 codec MCLK pin with 24.576MHz external oscillator audio o/p not observed in one Codec.
If we connect 2nd codec AD1939 codec MCLK pin with RX_HDMI clock (24.576MHz) audio o/p observed in 2nd codec.
AD1939A_MCLK_T <= OSC4_OUT_T; -- route MCLK output from Oscillator to AD1939A AD1939A_DBCLK_T <= SH_DAI0_P08_T; -- route SCLK generated by ADSP-21573 to AD1939A AD1939A_DLRCLK_T <= SH_DAI0_P09_T; -- route LRCLK generated by ADSP-21584 to AD1939A
AD1939B_MCLK_T <= ADV7625_AP1_OUT_MCLK_T; -- route MCLK output from RX_HDMI to AD1939BAD1939B_DBCLK_T <= SH_DAI0_P11_T; -- route SCLK generated by ADSP-21573 to AD1939BAD1939B_DLRCLK_T <= SH_DAI0_P12_T; -- route LRCLK generated by ADSP-21573 to AD1939B
-- TX_MCLK1 SH_DAI0_P10_T <= OSC4_OUT_T; -- connect 24.576 MHz OSC to TXMCLK2
Do we need to handle anything for Calculating PCG if we connect oscillator clock as input for PCG calculation and Audio codec(AD1939)
/**********PCG A calculation for Codec B************/
SRU(PCG0_CLKA_O,DAI0_PB11_I); SRU(PCG0_FSA_O,DAI0_PB12_I); SRU(LOW,DAI0_PBEN02_I); SRU(DAI0_PB02_O,PCG0_EXTCLKA_I); // MCLK to PCG A PCG_enable(A,0,0); PCG_Frame_Sync_set(A,1,512,256,4,1,0,0); PCG_Clockset(A,1,8,1,0,0); PCG_enable(A,1,1);
/***********PCG B calculation for Codec A*********/
SRU(LOW,DAI0_PBEN10_I); // TX_MCLK1 as clock input SRU(DAI0_PB10_O,PCG0_EXTCLKB_I); // External clock to PCG-C PCG_enable(B,0,0); PCG_Frame_Sync_set(B,1,512,256,4,1,0,0); // PCG B, PCG_Clockset(B,1,8,1,0,0); PCG_enable(B,1,1);
Hello ,As of my understanding if your expected output from PCG is 24.576MHz, you would need to bypass the PCG to output the 24.576MHz from the source of MCLK(24.576MHZ) which is fed to the PCGx Ext_input. I can see the clock divider value has set to '8' in the code and this will provide a 3.072 MHz output from PCG if the source is MCLK(24.576MHZ). To achieve your requirement, can you modify accordingly in the code as clock divider value to be a 0 in the PCG_Clockset(); API.Please let us know if my understanding went wrong.Regards,Lalitha