SEC CSID register as core MMR?

Question

Hi, 
 I am working on bringing up system interrupts on an ADSP-21571 processor. 
 There are hints in the manuals that the SEC0_CSIDn system memory mapped register (SMMR) is available as a core memory mapped register (CMMR), but I can't find it anywhere? 
 A proper SECI_ISR needs to access SEC0_CSDIn twice, and SEC0_END (another SMMR) once. 
 Having SEC0_CSIDn available as a CMMR would improve our interrupt latency greatly, since SMMR accesses take "38-60 cycles", but CMMR accesses give only "0-4 stall cycles". 
 /Johan

ADIApproved · Accepted Answer

Hi, Sorry for the delayed response. Please note that, Execution or data access from SMMR space can create problems, as many peripheral FIFOs are mapped in this space. To help programs detect any such accesses, the processor provides the illegal MMR access interrupt. This logic detects accesses both to core MMRs and to system MMRs. Setting the IIRAE bit in the MODE2 register enables this interrupt. 
 Please refer the PRM of ADSP-21571 for more information. Regards, Lalitha S)

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SEC CSID register as core MMR?