So I set CGU like so ...
By my reckoning, that configuration is:
SYS_CLKIN 25MHzCGU_CTL: DF = 0 CGU_CTL: MSEL = 18 PLLCLK = (SYS_CLKIN / (DF+1)) * MSEL (25MHz / 1) * 18 = 450MHzCGU_DIV: OSEL = 18 OCLK = (SYS_CLKIN / (DF+1)) * MSEL / OSEL (25MHz / 1) * 18 / 18 = 25MHzCGU_DIV: DSEL = 9 DCLK = (SYS_CLKIN / (DF+1)) * MSEL / DSEL (25MHz / 1) * 18 / 9 = 50MHzCGU_DIV: S1SEL = 2 SCLK1 = SYS_CLKIN / S1SEL (25MHz / 2) = 12.5MHzCGU_DIV: SYSSEL = 2 SYSCLK = (SYS_CLKIN / (DF+1)) * MSEL / SYSSEL (25MHz / 1) * 20 / 2 = 225MHzCGU_DIV: S0SEL = 2 SCLK0 = SYS_CLKIN / S0SEL (25MHz / 2) = 12.5MHzCGU_DIV: CSEL = 1 CCLK = (SYS_CLKIN / (DF+1)) * MSEL / CSEL (25MHz / 1) * 20 / 1 = 450MHz
In the HRM Introduction section, DMA is "Clocked by SCLK0 from CGU0 and SCLK1 from CGU1". In my configuration, SCLK0 is set to 12.5MHZ, is that the limit? I am trying to stream audio data from RAM to SPORT: 32 bits wide word * 2 * 384K. It works flawless at 192K, starts corrupting at 384K. Do I need a different clock configuration to set the DMA clock higher?
Hello,It seems there is no ADSP-21589 DSP available in the anlaog device. Is this typo? If yes, please confirm which processor are you using?Still I can suggest you to have a look at Clock Related Operating Conditions section (PageNo:81 / 173) in the datasheet of ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587.
As per the datasheet SCLK0 should be min 30 Mhz to Max 125 Mhz.
Please find the datasheet from below link,www.analog.com/.../ADSP-SC582_583_584_587_589_ADSP-21583_584_587.pdfRegards,Lalitha.S
Thanks for the reply. Yes it is a typo, we are using ADSP-21584. The datasheet answers my question, we are setting SCLK0 too low. I think we will have to use CGU0 and CGU1 to get all the clocks we need.
I made a mistake in the calculation of SCLK0 and SCLK1. With the correction, the DMA blocks are already getting fast clocks, and therefore, still have the original problem that 384K audio is corrupting, 192K is not.
CGU0_CTL: DF = 0: Pass SYS_CLKIN to PLL
CGU0_CTL: MSEL = 18: PLLCLK = (SYS_CLKIN / (DF+1)) * MSEL= (25MHz / 1) * 18= 450MHz
CGU0_DIV: CSEL = 1: CCLK = PLLCLK / CSEL= 450MHz / 1= 450MHz
CGU0_DIV: OSEL = 18: OUTCLK = PLLCLK / OSEL= 450MHz / 18= 25MHz
CGU0_DIV: DSEL = 9: DCLK = PLLCLK / DSEL= 450MHz / 9= 50MHz
CGU0_DIV: SYSSEL = 2: SYSCLK = PLLCLK / SYSSEL= 450MHz / 2= 225MHz
CGU0_DIV: S1SEL = 2: SCLK1 = SYSCLK / S1SEL= 225MHz / 2= 112.5MHz
CGU0_DIV: S0SEL = 2: SCLK0 = SYSCLK / S0SEL= 225MHz / 2= 112.5MHz
Hello,It seems you are working on Audio processing where the SPORT peripheral is used to transmit the sampled data in your custom board.However, I also like to know the more information about your end application and the issue which you are facing now?
Please confirm whether the issue is present on debugging time (or) booting time ?Regarding the issue, It would be helpful if you could share us the minimal project which would replicate the issue in ADSP-SC58x EZkit.Regards,Lalitha