ADSP-21589 DMA SGU clocking config?

So I set CGU like so ...

CGU0_CTL 00001200

CGU0_DIV 04894241

By my reckoning, that configuration is:


SYS_CLKIN 25MHz
CGU_CTL: DF = 0
CGU_CTL: MSEL = 18     PLLCLK = (SYS_CLKIN / (DF+1)) * MSEL (25MHz / 1) * 18 = 450MHz
CGU_DIV: OSEL = 18     OCLK = (SYS_CLKIN / (DF+1)) * MSEL / OSEL (25MHz / 1) * 18 / 18 = 25MHz
CGU_DIV: DSEL = 9     DCLK = (SYS_CLKIN / (DF+1)) * MSEL / DSEL (25MHz / 1) * 18 / 9 = 50MHz
CGU_DIV: S1SEL = 2     SCLK1 = SYS_CLKIN / S1SEL (25MHz / 2) = 12.5MHz
CGU_DIV: SYSSEL = 2     SYSCLK = (SYS_CLKIN / (DF+1)) * MSEL / SYSSEL (25MHz / 1) * 20 / 2 = 225MHz
CGU_DIV: S0SEL = 2     SCLK0 = SYS_CLKIN / S0SEL (25MHz / 2) = 12.5MHz
CGU_DIV: CSEL = 1     CCLK = (SYS_CLKIN / (DF+1)) * MSEL / CSEL (25MHz / 1) * 20 / 1 = 450MHz

In the HRM Introduction section, DMA is "Clocked by SCLK0 from CGU0 and SCLK1 from CGU1". In my configuration, SCLK0 is set to 12.5MHZ, is that the limit? I am trying to stream audio data from RAM to SPORT: 32 bits wide word * 2 * 384K. It works flawless at 192K, starts corrupting at 384K. Do I need a different clock configuration to set the DMA clock higher?

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