Are there any power sequencing requirement for SC57x or SC58x?
any sequencing requirements for DDR?
As per the datasheet, there are no power-up sequence requirements for SC57x/SC58x parts.
BUT, there is an anomaly applicable for both processor series that requires VDDINT to be within specification…
BUT, there is an anomaly applicable for both processor series that requires VDDINT to be within specification before ramping up VDDEXT (20000093 - Power-Up Sequencing May Cause Pins to Be Unexpectedly Driven).
This anomaly is fixed in silicon revisions SC58x/2158x rev 1.2 as well as in SC57x/2157x rev 0.2.
Please refer to the corresponding anomaly sheets for more details on this:
ADSP-SC58X/ADSP-2158X: Silicon Anomaly Sheet (Rev. D)
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Silicon Anomaly List for Revision(s) 0.0, 0.2 (Rev. D)
Are there any power ramp-up time requirement? In my design I'm going to use regulator with 200us soft start time. Is such time ok? I am a bit worried because this is ten times faster than soft start time on the EzKits.