I am using the SMC bus to move data between an SC587 and an FPGA and I am seeing some inconsistencies in the way the AMSx lines move when it comes to executing reads or writes on the ARM core vs the SHARC core. The code snippet below shows how I am configuring the SMC and attempting to perform a single 16-bit word read. When the read is executed on the ARM core, a single pulse of the AMS0 line occurs as expected. When the same read is executed on one of the SHARC cores, 32 pulses occur instead of one.
Is there reason for this difference in behavior and/or a way to make the SHARC cores perform reads/writes like the ARM core?
#define FPGA_DATA_ADDRESS (void *)0x40000000
* SMPU configured to enable secure reads and writes
*pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN
*pREG_SMC0_B0CTL = 0; // clear contents of SMC0 Bank 0 CTRL Register
*pREG_SMC0_B0TIM = 0x0F770F77;
*pREG_SMC0_B0ETIM = 0x00020200;
*pREG_SMC0_B0CTL = 0x00000101;
uint16_t test = *((uint16_t *)FPGA_DATA_ADDRESS);
Can you please share us the Scope capture showing data transfer for ARM and SHARC?
I actually just figured out the issue -
On the ARM, the default abstract page table sets the SMC memory as uncached.
The SHARC cores default the SMC memory as cached which seems to cause the weird behavior. I disabled caching for this region of memory with the SHL1C0 range registers and now reads/writes to the SMC perform as expected on the SHARC.
*pREG_SHL1C0_RANGE_START7 = 0x40000000; //Beginning of SMC Bank 0
*pREG_SHL1C0_RANGE_END7 = 0x4FFFFFFF; //End of SMC Bank 3
*pREG_SHL1C0_CFG2 |= BITM_SHL1C_CFG2_RR7EN | BITM_SHL1C_CFG2_RR7SEL;
Glad! Thanks for your update