SC587 SMC read/writes behaving differently when executed on ARM core vs SHARC core

I am using the SMC bus to move data between an SC587 and an FPGA and I am seeing some inconsistencies in the way the AMSx lines move when it comes to executing reads or writes on the ARM core vs the SHARC core. The code snippet below shows how I am configuring the SMC and attempting to perform a single 16-bit word read. When the read is executed on the ARM core, a single pulse of the AMS0 line occurs as expected. When the same read is executed on one of the SHARC cores, 32 pulses occur instead of one.  

Is there reason for this difference in behavior and/or a way to make the SHARC cores perform reads/writes like the ARM core? 

#define	FPGA_DATA_ADDRESS			(void *)0x40000000
	
void smc_example()
{	
	/*
	 * SMPU configured to enable secure reads and writes
	 */
	*pREG_SMPU0_SECURECTL = (ENUM_SMPU_SECURECTL_WSECEN
			|ENUM_SMPU_SECURECTL_WNSDIS
			| ENUM_SMPU_SECURECTL_RSECEN
			| ENUM_SMPU_SECURECTL_RNSDIS
			| ENUM_SMPU_SECURECTL_SBEDIS);

	*pREG_SMC0_B0CTL = 0;	// clear contents of SMC0 Bank 0 CTRL Register
	*pREG_SMC0_B0TIM = 0x0F770F77;
	*pREG_SMC0_B0ETIM = 0x00020200;
	*pREG_SMC0_B0CTL = 0x00000101;
	
	uint16_t test = *((uint16_t *)FPGA_DATA_ADDRESS);

}