ADSP-SC58x/2158x PMU Overflow Interrupt- Example code

Attached code is an example of configuring the interrupt for Performance Monitor Unit cycle count overflow. This code runs in Cortex A5 in ADSP-SC58x processor.

PMU_Overflow_Interrupt_Core0.zip
  • Hi,
            I'm trying to get the cycle counts for particular function in Cortex A5 (ADSP-SC589). I have used the following three ways,
            Way1: Using GP Timer in continuous PWM mode.
               SET_TIMER_ARM();
                    for (j=0;j<5;j++)
                    {
                        int a=5,b=10,sum;
                        sum=a+b;
                    }
                CALCULATE_MIPS_ARM();
            
            Way2: Using Core Cycle-Counting Macros
                CCNTR_INIT;
                CCNTR_START;
                    for (j=0;j<5;j++)
                    {
                        int a=5,b=10,sum;
                        sum=a+b;
                    }            
                CCNTR_STOP;
                CCNTR_READ;
                
            Way3: Using A5_PMU source files which is attached in this discussion.
                A5_Start_Cycle_Count();
                    for (j=0;j<5;j++)
                    {
                        int a=5,b=10,sum;
                        sum=a+b;
                    }        
                A5_Stop_Cycle_Count();
                A5_Print_CCNT_Count_Values();

    All the three ways provides different cycle counts. In Cortex A5, NOP does not have to consume clock cycles, but Way 2&3 provides large cycle counts for NOP only. Way1 provides Zero cycle count for NOP, but that method has interrupts.

    Can you please suggest which one is accurate and better method?


    Can you provide the example cycle count measure code for Core0 without interrupt?