Post Go back to editing

Is there an error detection support for A5 core L1Cache RAM in ADSP-SC57x processor ?

Yes. ARM L1Cache RAM is provided with single bit error detection support. A single parity error status signal will be given out and a parity interrupt can be generated and routed to any of the the three cores by configuring the appropriate registers in MEC. An example code for enabling this parity interrupt is attached.

ARM_L1_Parity_Core0.c.zip