As SHARC cores executing via core clock, the DMA and the movement from FIFO to internal registers are all at SCLK frequency, because of this there should not be any delay between the cores as per the below block.
NOTES: Using DMA SYNC bit is important to synchronize between peripheral requests and DMA.
You can refer to the below FAQ link for ADSP-SC58x Multicore SPORT TDM example project
https://ez.analog.com/dsp/sharc-processors/adsp-sc5xxadsp-215xx/w/documents/32397/adsp-sc58x-multicore-sport-tdm-example