Yes. Mainly the conditional branches are impacted by the increase in the number of stalls caused by increase in the number of pipeline stages from 5 to 11 stage.
This is mitigated by the addition of…
The CCES Run-time libraries are in the process of being optimized and to date about 70% of the libraries are optimized. We will update this thread once all the libraries are optimized.
All core interrupts will be programmed through the IRPTL, IMASK and IMASKP registers. But SHARC+ Core does not have LIRPTL register(This was present in the SHARC Core).
IRPTL register bit association…
Yes, the following are the new Core interrupts in SHARC+ Core (These are in addition to the already existing core interrupts in SHARC core)
L1 Parity Error (PARI)
Illegal Opcode Detection error…
If the prediction is found to be correct, then it saves a number of stalls, but if it is found to be incorrect then the pipeline will face the same number of stalls as it would have faced without branch…
Yes, Hardware loops do exist in SHARC+ Core. This special piece of hardware execute zero or low-overhead loops
SHARC+ Core has both, Counter based Loop and Arithmetic Loop, same as SHARC Core and one…
All the DMA engines view SHARC’s L1 memory space from System View as Byte Addressable space.
For example SHARC0’s L1 Block 0 SRAM start address for a data byte access is 0x0024_0000.
In system view…
With the increase in the number of pipeline stages, change of flow (COF) become more costly to the processor’s performance due to the increased number of pipeline flushes and stalls. Branch Target Buffer…
There is a difference in the way the self-modifying codes has to be written in SHARC and SHARC+ core , and if you are porting the ‘asm’ code from previous SHARC , it is worth taking care of this new restriction…
