How to phase shift two PCG CLK outputs?

Hello,

I cannot figure out how to setup two PCGs (e.g., PCG_A and PCG_B) to generate the following timings (TDM8 and I2S perfectly in phase):

This looks to be impossible to achieve even with the following settings:

// I2S
ClkConfig.bExternalTrigger=0;
ClkConfig.eClkInput=ADI_PCG_CLK_EXT;
ClkConfig.nDiv=8;
FsConfig.bExternalTrigger=0;
FsConfig.eClkInput=ADI_PCG_CLK_EXT;
FsConfig.eFsBypassMode=ADI_PCG_FSBYPASS_MODE_NORMAL;
FsConfig.nDiv=512;
FsConfig.nPhase=4+256;
FsConfig.nPulseWidth=256;
adi_pcg_Init(ADI_PCG_DEV_A,&ClkConfig,&FsConfig);

// TDM8
ClkConfig.bExternalTrigger=0;
ClkConfig.eClkInput=ADI_PCG_CLK_EXT;
ClkConfig.nDiv=2;
FsConfig.bExternalTrigger=0;
FsConfig.eClkInput=ADI_PCG_CLK_EXT;
FsConfig.eFsBypassMode=ADI_PCG_FSBYPASS_MODE_NORMAL;
FsConfig.nDiv=512;
FsConfig.nPhase=1;
FsConfig.nPulseWidth=256;
adi_pcg_Init(ADI_PCG_DEV_B,&ClkConfig,FsConfig);

leading to the following output waveforms:

in which, as you can see, the relative timings between FS and BCK of each respective audio bus is respected, but not the timing between the two FS signals nor the desired phase alignment between BCK edges (a falling edge in I2S BCK signal always corresponds to a rising edge in TDM BCK signal).

Since CLK outs of both PCG_A and PCG_B are always derived by dividing the same external clock source (OSC IC) it looks impossible to arbitrarily shift one BCK respectfully to another one (e.g., BCK falling edge of PCG_A will always occur during a rising edge of BCK outputted by PCG_B). The situation is even more complicated when trying to synchronize and relatively shift clocks generated by PCGs located in different DAI domains.

P.S.

I'm also able, obvs, to obtain the following result by setting I2S phase shift to 256 + 1 instead of 256 + 4, but the problem in the subject remains: I'm completely unable to shift BCK outputs, then I2S BCK rising/falling edges are always occurring during TDM8 BCK rising edges.